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IMP1232LPS-2 Datasheet(PDF) 5 Page - IMP, Inc |
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IMP1232LPS-2 Datasheet(HTML) 5 Page - IMP, Inc |
5 / 7 page © 1999 IMP, Inc. 408-432-9100/www.impweb.com 5 IMP1 IMP1232LP/LPS 232LP/LPS Application Information Figure 6. Application Circuit: Watchdog Timer Watchdog Timer and ST Input A watchdog timer stops and restarts a microprocessor that is “hung-up”. Through the time delay input, TD, three watchdog time-out periods are selectable: 150ms, 610ms and 1,200ms. If the strobe input, ST, is not strobed LOW prior to timeout, reset signals become active. On power-up or after the supply voltage returns to an in-tolerance condition, the reset signal remains active for 250ms minimum, allowing the power supply and system micro- processor to stabilize. ST Pulses as short as 20ns can be detected. Figure 5. Timing Diagram: Strobe Input RESET ST Valid Strobe Valid Strobe Invalid Strobe tRST tST Note: ST is ignored whenever a reset is active. tTD (Min) tTD (Max) 1232_09.eps A HIGH-to-LOW ST signal transition must be regularly issued no later than the minimum time-out period defined by the state of the TD signal. This guarantees the watchdog timer does not time-out. Timeouts periods of approximately 150ms, 610ms or 1,200ms are selected through the TD pin. 1232_07.eps PBRST 5V 1 10k Ω VCC TD 2 ST TOL IMP1232LP/LPS µP Decoder 3 4 RESET GND 8 7 6 5 RESET MREQ Address Bus RESET l e v e L e g a t l o V D T ) s m ( d o i r e P t u O - e m i T g o d h c t a W n i Ml a n i m o Nx a M D N G5 . 2 60 5 10 5 2 g n i t a o l F0 5 20 1 60 0 0 1 V C C 0 0 50 0 2 10 0 0 2 s p e . 3 0 t _ 2 3 2 1 The watchdog timer cannot be disabled. It must be strobed with a high-to-low transition to avoid a watchdog timeout. |
Similar Part No. - IMP1232LPS-2 |
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Similar Description - IMP1232LPS-2 |
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