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IDT54FCT377ATSOB Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT54FCT377ATSOB Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 7 page Integrated Device Technology, Inc. DESCRIPTION: The IDT54/74FCT377T/AT/CT/DT are octal D flip-flops built using an advanced dual metal CMOS technology. The IDT54/ 74FCT377T/AT/CT/DT have eight edge-triggered, D-type flip- flops with individual D inputs and O outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously when the Clock Enable ( CE) is LOW. The register is fully edge-triggered. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s O output. The CE input must be stable only one set-up time prior to the LOW-to-HIGH transi- tion for predictable operation. IDT54/74FCT377T/AT/CT/DT FAST CMOS OCTAL D FLIP-FLOP WITH CLOCK ENABLE MILITARY AND COMMERCIAL TEMPERATURE RANGES APRIL 1995 ©1995 Integrated Device Technology, Inc. 6.14 DSC-4200/3 1 The IDT logo is a registered trademark of Integrated Device Technology, Inc. FEATURES: • Std., A, C and D speed grades • Low input and output leakage ≤1µA (max.) • CMOS power levels • True TTL input and output compatibility – VOH = 3.3V (typ.) – VOL = 0.3V (typ.) • High drive outputs (-15mA IOH, 48mA IOL) • Power off disable outputs permit “live insertion” • Meets or exceeds JEDEC standard 18 specifications • Product available in Radiation Tolerant and Radiation Enhanced versions • Military product compliant to MIL-STD-883, Class B and DESC listed (dual marked) • Available in DIP, SOIC, QSOP, CERPACK and LCC packages 2630 drw 01 CE CP D CP Q D 0 O 0 D CP Q D 1 O1 D CP Q D 2 O 2 D CP Q D 3 O 3 D CP Q D 4 O 4 D CP Q D 5 O 5 D CP Q D 6 O6 D CP Q D 7 O 7 FUNCTIONAL BLOCK DIAGRAM |
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