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IDT7MB4145S20M Datasheet(PDF) 4 Page - Integrated Device Technology |
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IDT7MB4145S20M Datasheet(HTML) 4 Page - Integrated Device Technology |
4 / 8 page IDT7MP4045/7MP4145 256K x 32 CMOS STATIC RAM MODULE COMMERCIAL TEMPERATURE RANGE 15.2 4 AC ELECTRICAL CHARACTERISTICS (VCC = 5V ±10%, TA = 0°C to +70°C) ’4045SxxZ, ’4045/4145SxxM –15 –20 Symbol Parameter Min. Max. Min. Max. Unit Read Cycle tRC Read Cycle Time 15 — 20 — ns tAA Address Access Time — 15 — 20 ns tACS Chip Select Access Time — 15 — 20 ns tCLZ (1) Chip Select to Output in Low-Z 3 — 5 — ns tOE Output Enable to Output Valid — 8 — 10 ns tOLZ (1) Output Enable to Output in Low-Z 0 — 0 — ns tCHZ (1) Chip Deselect to Output in High-Z — 8 — 10 ns tOHZ (1) Output Disable to Output in High-Z — 8 — 10 ns tOH Output Hold from Address Change 3 — 3 — ns tPU (1) Chip Select to Power-Up Time 0 — 0 — ns tPD (1) Chip Deselect to Power-Down Time — 15 — 20 ns Write Cycle tWC Write Cycle Time 15 — 20 — ns tCW Chip Select to End-of-Write 12 — 15 — ns tAW Address Valid to End-of-Write 12 — 15 — ns tAS Address Set-up Time 0 — 0 — ns tWP Write Pulse Width 12 — 15 — ns tWR Write Recovery Time 0 — 0 — ns tWHZ (1) Write Enable to Output in High-Z — 8 — 13 ns tDW Data to Write Time Overlap 10 — 12 — ns tDH Data Hold from Write Time 0 — 0 — ns tOW (1) Output Active from End-of-Write 0 — 0 — ns NOTE: 2703 tbl 11 1. This parameter is guaranteed by design but not tested. |
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