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March 28, 2000

IDT79RC4650™

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The following is a list of interface, interrupt, and miscellaneous pins available on the RC4650. Pins marked with one asterisk are active when low.

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System interface:

ExtRqst*

Input

External request

Signals that the system interface needs to submit an external request.

Release*

Output

Release interface

Signals that the processor is releasing the system interface to slave state

RdRdy*

Input

Read Ready

Signals that an external agent can now accept a processor read.

WrRdy*

Input

Write Ready

Signals that an external agent can now accept a processor write request.

ValidIn*

Input

Valid Input

Signals that an external agent is now driving a valid address or data on the SysAD bus and a valid com-

mand or data identifier on the SysCmd bus.

ValidOut*

Output

Valid output

Signals that the processor is now driving a valid address or data on the SysAD bus and a valid command

or data identifier on the SysCmd bus.

SysAD(63:0)

Input/Output

System address/data bus

A 64-bit address and data bus for communication between the processor and an external agent.

SysADC(7:0)

Input/Output

System address/data check bus

An 8-bit bus containing parity check bits for the SysAD bus during data bus cycles.

SysCmd(8:0)

Input/Output

System command/data identifier bus

A 9-bit bus for command and data identifier transmission between the processor and an external agent.

SysCmdP

Input/Output

Reserved system command/data identifier bus parity

For the RC4650 this signal is unused on input and zero on output.

Clock/control interface:

MasterClock

Input

Master clock

Master clock input used as the system interface reference clock. All output timings are relative to this input

clock. Pipeline operation frequency is derived by multiplying this clock up by the factor selected during

boot initialization.

Input

Quiet VCC for PLL

Input

Quiet VSS for PLL

Interrupt interface:

Int*(5:0)

Input

Interrupt

Six general processor interrupts, bit-wise ORed with bits 5:0 of the interrupt register.

NMI*

Input

Non-maskable interrupt

Non-maskable interrupt, ORed with bit 6 of the interrupt register.