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IDT54FCT810CTSOB Datasheet(PDF) 5 Page - Integrated Device Technology |
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IDT54FCT810CTSOB Datasheet(HTML) 5 Page - Integrated Device Technology |
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5 / 6 page  IDT54/74FCT810BT/CT FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES 9.4 5 NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH 2. Pulse Generator for All Pulses: f ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns Package 1 and Package 2 are same device type and speed grade 3103 drw 10 3103 drw 09 OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH CONTROL INPUT 3V 1.5V 0V 3.5V 0V SWITCH CLOSED SWITCH OPEN VOL VOH 0.3V 0.3V t PLZ t PZL t PZH t PHZ 3.5V 0V 1.5V 1.5V ENABLE DISABLE tPD1a PACKAGE 1 OUTPUT PACKAGE 2 OUTPUT tSK2(o) tPD2a 3V 0V VOH 1.5V 1.5V VOL VOH 1.5V VOL INPUT tPD1b tPD2b tSK2(o) tSK(t) = |tPD2a - tPD1a| or |tPD2b- tPD1b| PACKAGE SKEW - tSK(t) ENABLE AND DISABLE TIMES DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. TEST CIRCUITS AND WAVEFORMS TEST CIRCUIT FOR ALL OUTPUTS ENABLE AND DISABLE TIME SWITCH POSITION Test Switch Disable LOW Enable LOW Closed Disable HIGH Enable HIGH Open 3103 lnk 07 Pulse Generator R T D.U.T. VCC VIN C L V OUT 50pF 500 Ω 500 Ω 7.0V 3103 drw 04 3103 drw 07 3103 drw 08 tPLH tPHL 3V 0V VOH 1.5V 1.5V VOL tSK(p) = |tPHL - tPLH| INPUT OUTPUT tPLH1 OUTPUT 1 OUTPUT 2 tSK2(o) tPHL2 3V 0V VOH 1.5V 1.5V VOL VOH 1.5V VOL INPUT tPHL1 tPLH2 tSK2(o) tSK2(o) = |tPHL2 - tPLH1| or |tPLH2 - tPHL1| 3103 drw 06 3103 drw 05 TEST WAVEFORMS PACKAGE DELAY 3V 0V VOH tPLH tPHL VOL 1.5V 1.5V tR tF 2.0V 0.8V tPLH1 OUTPUT 1 OUTPUT 2 tSK1(o) tPLH2 3V 0V VOH 1.5V 1.5V VOL VOH 1.5V VOL INPUT tPHL1 tPHL2 tSK1(o) tSK1(o) = |tPLH2 - tPLH1| or |tPHL2 - tPLH1| INPUT OUTPUT OUTPUT SKEW (ALL BANKS) - tSK2(o) PULSE SKEW - tSK(p) OUTPUT SKEW (SAME BANK) - tSK1(o) |
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