IDT54/74FCT388915T 70/100/133/150

3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

9.8

2

PIN CONFIGURATIONS

PLCC/LCC

TOP VIEW

PIN DESCRIPTION

SSOP

TOP VIEW

3052 drw 03

5

6

7

8

9

10

OE/RST

FEEDBACK

1

2

3

4

20

19

18

17

16

15

14

13

Q4

12

11

GND

Q/2

REF_SEL

SYNC(0)

LF

GND

Q3

Q2

GND

GND(AN)

LOCK

Q5

2Q

SO28-7

21

22

23

24

SYNC(1)

FREQ_SEL

GND

Q0

Q1

GND

PLL_EN

25

26

27

28

Q/2

GND

Q3

Q2

GND

LOCK

FEEDBK

REF_SEL

SYNC(0)

LF

GND(AN)

SYNC(1)

28

4

3

2

1

27

26

25

24

23

22

21

20

19

5

6

7

8

9

10

11

12

13

14

15

16

17

18

J28-1,

L28-1

3052 drw 02

Pin Name

I/O

Description

SYNC(0)

I

Reference clock input.

SYNC(1)

I

Reference clock input.

REF_SEL

I

Chooses reference between SYNC (0) & SYNC (1). (Refer to functional block diagram).

FREQ_SEL

I

Selects between

÷ 1 and ÷ 2 frequency options. (Refer to functional block diagram).

FEEDBACK

I

Feedback input to phase detector.

LF

I

Input for external loop filter connection.

Q0-Q4

O

Clock output.

Q5

O

Inverted clock output.

2Q

O

Clock output (2 x Q frequency).

Q/2

O

Clock output (Q frequency

÷ 2).

LOCK

O

Indicates phase lock has been achieved (HIGH when locked).

OE/

RST

I

Asynchronous reset (active LOW) and output enable (active HIGH). When HIGH, outputs are

enabled. When LOW, outputs are in HIGH impedance.

PLL_EN

I

Disables phase-lock for low frequency testing. (Refer to functional block diagram).

3052 tbl 01