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IDT72420L35TPB Datasheet(PDF) 2 Page - Integrated Device Technology |
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IDT72420L35TPB Datasheet(HTML) 2 Page - Integrated Device Technology |
2 / 16 page 5.12 2 IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO ™ 64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8 MILITARY AND COMMERCIAL TEMPERATURE RANGES PIN CONFIGURATION Symbol Name I/O Description D0 - D7 Data Inputs I Data inputs for a 8-bit bus. RS Reset I When RS is set LOW, internal read and write pointers are set to the first location of the RAM array, FF and AF go HIGH, and AE and EF go LOW. A reset is required before an initial WRITE after power-up. WCLK Write Clock I Data is written into the FIFO on a LOW-to-HIGH transition of WCLK when WEN is asserted. WEN Write Enable I When WEN is LOW, data is written into the FIFO on every LOW-to-HIGH transition of WCLK. Data will not be written into the FIFO if the FF is LOW. Q0 - Q7 Data Outputs O Data outputs for a 8-bit bus. RCLK Read Clock I Data is read from the FIFO on a LOW-to-HIGH transition of RCLK when REN is asserted. REN Read Enable I When REN is LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK. Data will not be read from the FIFO if the EF is LOW. OE Output Enable I When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will be in a high-impedance state. EF Empty Flag O When EF is LOW, the FIFO is empty and further data reads from the output are inhibited. When EF is HIGH, the FIFO is not empty. EF is synchronized to RCLK. AE Almost-Empty O When AE is LOW, the FIFO is almost empty based on the offset Empty+7. AE is synchronized Flag to RCLK. AF Almost-Full Flag O When AF is LOW, the FIFO is almost full based on the offset Full-7. AF is synchronized to WCLK. FF Full Flag O When FF is LOW, the FIFO is full and further data writes into the input are inhibited. When FF is HIGH, the FIFO is not full. FF is synchronized to WCLK. VCC Power One +5 volt power supply pin. GND Ground One 0 volt ground pin. PIN DESCRIPTIONS 2680 tbl 01 DIP TOP VIEW D5 P28-2 C28-1 2680 drw 02 VCC Q1 Q2 Q3 Q4 Q5 Q6 Q7 WCLK RS D7 D6 WEN 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Q0 FF EF OE REN RCLK GND AE AF D0 D1 D2 D3 D4 14 13 12 11 10 9 8 7 6 5 4 3 2 1 |
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