Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AUGUST 1996

©1996 Integrated Device Technology, Inc.

5.4

DSC-3032/6

IDT54/74FCT16260AT/CT/ET

IDT54/74FCT162260AT/CT/ET

1

FAST CMOS

12-BIT TRI-PORT

BUS EXCHANGER

FEATURES:

• Common features:

–

0.5 MICRON CMOS Technology

–

High-speed, low-power CMOS replacement for

ABT functions

–

–

Low input and output leakage

≤1µA (max.)

–

ESD > 2000V per MIL-STD-883, Method 3015;

> 200V using machine model (C = 200pF, R = 0)

–

Packages include 25 mil pitch SSOP, 19.6 mil pitch

TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack

–

Extended commercial range of -40

°C to +85°C

±10%

• Features for FCT16260AT/CT/ET:

–

–

Power off disable outputs permit “live insertion”

–

°C

• Features for FCT162260AT/CT/ET:

–

Balanced Output Drivers:

±24mA (commercial),

±16mA (military)

–

Reduced system switching noise

–

°C

DESCRIPTION:

The FCT16260AT/CT/ET and the FCT162260AT/CT/ET

Tri-Port Bus Exchangers are high-speed 12-bit latched bus

multiplexers/transceivers for use in high-speed microproces-

sor applications. These Bus Exchangers support memory

interleaving with latched outputs on the B ports and address

multiplexing with latched inputs on the B ports.

The Tri-Port Bus Exchanger has three 12-bit ports. Data

may be transferred between the A port and either/both of the

B ports. The latch enable (LE1B, LE2B, LEA1B and LEA2B)

inputs control data storage. When a latch-enable input is

HIGH, the latch is transparent. When a latch-enable input is

LOW, the data at the input is latched and remains latched until

the latch enable input is returned HIGH. Independent output

enables (

OE1B and OE2B) allow reading from one port while

writing to the other port.

The FCT16260AT/CT/ET are ideally suited for driving high

capacitance loads and low impedance backplanes.

The

output buffers are designed with power off disable capability

to allow "live insertion" of boards when used as backplane

drivers.

The FCT162260AT/CT/ET have balanced output drive

with current limiting resistors. This offers low ground bounce,

minimal undershoot, and controlled output fall times - reduc-

ing the need for external series terminating resistors.

A-1B

LATCH

LEA1B

LE1B

LE2B

12

M

U

X

12

OE1B

12

1B-A

LATCH

12

12

12

2B-A

LATCH

12

12

A-2B

LATCH

LEA2B

12

OE2B

OEA

SEL

1

0

3032 drw 01

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

FUNCTIONAL BLOCK DIAGRAM