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IDT74FCT162652ATPA Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT74FCT162652ATPA Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 9 page Integrated Device Technology, Inc. The IDT logo is a registered trademark of Integrated Device Technology, Inc. MILITARY AND COMMERCIAL TEMPERATURE RANGE AUGUST 1996 ©1996 Integrated Device Technology, Inc. DSC-2549/8 1 IDT54/74FCT16652T/AT/CT/ET IDT54/74FCT162652T/AT/CT/ET FAST CMOS 16-BIT BUS TRANSCEIVER/ REGISTERS FEATURES: • Common features: – 0.5 MICRON CMOS Technology – High-speed, low-power CMOS replacement for ABT functions – Typical tSK(o) (Output Skew) < 250ps – Low input and output leakage ≤1µA (max.) – ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) – Packages include 25 mil pitch SSOP, 19.6 mil pitch TSSOP,15.7 mil pitch TVSOP and 25 mil pitch Cerpack – Extended commercial range of -40 °C to +85°C –VCC = 5V ±10% • Features for FCT16652T/AT/CT/ET: – High drive outputs (-32mA IOH, 64mA IOL) – Power off disable outputs permit “live insertion” – Typical VOLP (Output Ground Bounce) < 1.0V at VCC = 5V, TA = 25 °C • Features for FCT162652T/AT/CT/ET: – Balanced Output Drivers: ±24mA (commercial), ±16mA (military) – Reduced system switching noise – Typical VOLP (Output Ground Bounce) < 0.6V at VCC = 5V,TA = 25 °C DESCRIPTION: The FCT16652T/AT/CT/ET and FCT162652T/AT/CT/ET 16-bit registered transceivers are built using advanced dual metal CMOS technology. These high-speed, low-power de- vices are organized as two independent 8-bit bus transceivers with 3-state D-type registers. For example, the xOEAB and x OEBA signals control the transceiver functions. The xSAB and xSBA control pins are provided to select either real time or stored data transfer. The circuitry used for select control will eliminate the typical decoding glitch that occurs in a multiplexer during the transition between stored and real time data. A LOW input level selects real-time data and a HIGH level selects stored data. Data on the A or B data bus, or both, can be stored in the internal D-flip-flops by LOW-to-HIGH transitions at the appro- priate clock pins (xCLKAB or xCLKBA), regardless of the select or enable control pins. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin. The FCT16652T/AT/CT/ET are ideally suited for driving high capacitance loads and low-impedance backplanes. The output buffers are designed with power off disable capability to allow "live insertion" of boards when used as backplane drivers. The FCT162652T/AT/CT/ET have balanced output drive with current limiting resistors. This offers low ground bounce, minimal undershoot, and controlled output fall times–reducing the need for external series terminating resistors. The FCT162652T/AT/CT/ET are plug-in replacements for the FCT16652T/AT/CT/ET and ABT16652 for on-board bus inter- face applications. FUNCTIONAL BLOCK DIAGRAM 1 A1 1 OEBA 1 CLKBA 1 SBA 1 CLKAB 1 SAB 1 OEAB 2549 drw 01 1 B1 B REG A REG D C C D TO 7 OTHER CHANNELS 2 B1 2 CLKAB 2 OEBA 2 CLKBA 2 SBA 2 A1 2 OEAB 2 SAB 2549 drw 02 TO 7 OTHER CHANNELS B REG A REG D C C D |
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