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IDT54FCT521SO Datasheet(PDF) 5 Page - Integrated Device Technology |
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IDT54FCT521SO Datasheet(HTML) 5 Page - Integrated Device Technology |
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5 / 6 page  5 IDT54/74FCT521/A/B/C FAST CMOS 8-BIT IDENTITY COMPARATOR MILITARYANDCOMMERCIALTEMPERATURERANGES Pulse Generator R T D.U.T. V CC V IN C L V OUT 50pF 500 Ω 500 Ω 7.0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V DATA IN PU T TIM IN G IN PU T ASYNCHRON OUS C ONTROL PRES ET CLEAR ETC. SYNC HRO N OU S CON TRO L tSU tH tREM tSU tH HIGH-LOW -HIGH PULSE LO W -H IGH -LOW PULSE tW 1.5V 1.5V SAM E PHASE IN PU T TR ANSITION 3V 1.5V 0V 1.5V VOH tPLH OU TPUT OPPOSITE P HASE IN PU T TR ANSITION 3V 1.5V 0V tPLH tPHL tPHL VOL CO NTR OL IN PU T 3V 1.5V 0V 3.5V 0V OU TPUT NO RM A LLY LO W OU TPUT NO RM A LLY HIGH SW ITC H CLOSE D SW ITC H OPEN VOL 0.3V 0.3V tPLZ tPZL tPZH tPHZ 3.5V 0V 1.5V 1.5V ENAB LE DISA BLE VOH PRES ET CLEAR CLOC K ENABLE ETC. Octal lin k Octal lin k Octal lin k Octal lin k Octal lin k TEST CIRCUITS AND WAVEFORMS PROPAGATION DELAY TEST CIRCUITS FOR ALL OUTPUTS ENABLE AND DISABLE TIMES SET-UP, HOLD, AND RELEASE TIMES PULSE WIDTH SWITCH POSITION Test Switch Open Drain Disable Low Closed Enable Low All Other Tests Open 8-link DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; Zo ≤ 50Ω; tF ≤ 2.5ns; tR ≤ 2.5ns. |
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