IDT54FCT388915T150 datasheet(8/11 Pages) IDT

Part #	IDT54FCT388915T150

Description	3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER WITH (3-STATE)

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Manufacturer	IDT [Integrated Device Technology]

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IDT54/74FCT388915T 70/100/133/150

3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER

MILITARY AND COMMERCIAL TEMPERATURE RANGES

9.8

8

The frequency relationship shown here is applicable to all Q

outputs (Q0, Q1, Q2, Q3 and Q4).

1:2 INPUT TO "Q" OUTPUT FREQUENCY RELATION-

SHIP

In this application, the Q/2 output is connected to the

FEEDBACK input. The internal PLL will line up the positive

edges of Q/2 and SYNC, thus the Q/2 frequency will equal the

SYNC frequency. The Q outputs (Q0-Q4,

Q5) will always run

at 2X the Q/2 frequency, and the 2Q output will run at 4X the

Q/2 frequency.

1:1 INPUT TO "Q" OUTPUT FREQUENCY RELATION-

SHIP

In this application, the Q4 output is connected to the

FEEDBACK input. The internal PLL will line up the positive

edges of Q4 and SYNC, thus the Q4 frequency (and the rest

of the "Q" outputs) will equal the SYNC frequency. The Q/2

output will always run at 1/2 the Q frequency, and the 2Q

output will run at 2X the Q frequency.

Q/2

Q3

Q2

PLL_EN

Q1

Q0

FQ_SEL

FEEDBACK

REF_SEL

SYNC(0)

VCC(AN)

LF

GND(AN)

Q4

Q5

2Q

FCT388915T

LOW

50 MHz signal

25 MHz feedback signal

HIGH

25 MHz

"Q"

Clock

Outputs

25 MHz

input

12.5 MHz

signal

OE/RST

3052 drw 10

Allowable Input Frequency Range:

40MHz to (f2Q MAX Spec) (for FREQ_SEL HIGH)

20MHz to (f2Q MAX Spec)/2 (for FREQ_SEL LOW)

Allowable Input Frequency Range:

20MHz to (f2Q MAX Spec)/2 (for FREQ_SEL HIGH)

10MHz to (f2Q MAX Spec)/4 (for FREQ_SEL LOW)

2:1 INPUT TO "Q" OUTPUT FREQUENCY RELATION-

SHIP

In this application, the 2Q output is connected to the

FEEDBACK input. The internal PLL will line up the positive

edges of 2Q and SYNC, thus the 2Q frequency will equal the

SYNC frequency. The Q/2 output will always run at 1/4 the

2Q frequency, and the Q output will run at 1/2 the 2Q

frequency.

Q/2

Q3

Q2

PLL_EN

Q1

Q0

FQ_SEL

FEEDBACK

REF_SEL

SYNC(0)

VCC(AN)

LF

GND(AN)

Q4

Q5

2Q

FCT388915T

LOW

50 MHz feedback signal

HIGH

25 MHz

"Q"

Clock

Outputs

50 MHz

input

12.5 MHz

input

OE/RST

3052 drw 11

Figure 3a. Wiring Diagram and Frequency Relationships With Q/2

Output Feedback

Figure 3c. Wiring Diagram and Frequency Relationships With 2Q

Output Feedback

Figure 3b. Wiring Diagram and Frequency Relationships With Q4

Output Feedback

Q/2

Q3

Q2

PLL_EN

Q1

Q0

FQ_SEL

FEEDBACK

REF_SEL

SYNC(0)

VCC(AN)

LF

GND(AN)

Q4

Q5

2Q

FCT388915T

LOW

50 MHz signal

12.5 MHz feedback signal

HIGH

25 MHz

"Q"

Clock

Outputs

12.5 MHz

input

OE/RST

3052 drw 09

Allowable Input Frequency Range:

10MHz to ( f2Q MAX Spec)/4 (for FREQ_SEL HIGH)

5MHz to (f2Q MAX Spec)/8 (for FREQ_SEL LOW)

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IDT54FCT388915T150 Datasheet(PDF) 8 Page - Integrated Device Technology

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