IDT7202LA40TD datasheet(6/13 Pages) IDT

Part #	IDT7202LA40TD

Description	CMOS ASYNCHRONOUS FIFO 256 x 9, 512 x 9, 1,024 x 9

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Manufacturer	IDT [Integrated Device Technology]

Direct Link	http://www.idt.com

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IDT7200/7201A/7202A CMOS ASYNCHRONOUS FIFO

256 x 9, 512 x 9 and 1,024 x 9

MILITARY, INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES

ongoing write operations. After Read Enable (

R) goes high,

the Data Outputs (Q0 – Q8) will return to a high impedance

condition until the next Read operation. When all data has

been read from the FIFO, the Empty Flag (

EF) will go low,

allowing the “final” read cycle but inhibiting further read

operations with the data outputs remaining in a high imped-

ance state. Once a valid write operation has been accom-

plished, the Empty Flag (

EF) will go high after tWEF and a valid

Read can then begin. When the FIFO is empty, the internal

read pointer is blocked from

R so external changes in R will not

affect the FIFO when it is empty.

FIRST LOAD/RETRANSMIT (

FL

FL/RT

RT)

This is a dual-purpose input. In the Depth Expansion Mode,

this pin is grounded to indicate that it is the first loaded (see

Operating Modes). In the Single Device Mode, this pin acts as

the restransmit input. The Single Device Mode is initiated by

grounding the Expansion In (

XI).

The IDT7200/7201A/7202A can be made to retransmit

data when the Retransmit Enable control (

RT) input is pulsed

low. A retransmit operation will set the internal read pointer to

the first location and will not affect the write pointer. Read

Enable (

R) and Write Enable (W) must be in the high state

during retransmit. This feature is useful when less than 256/

512/1,024 writes are performed between resets. The retrans-

mit feature is not compatible with the Depth Expansion Mode

and will affect the Half-Full Flag (

HF), depending on the

relative locations of the read and write pointers.

EXPANSION IN (

XI

XI)

This input is a dual-purpose pin.

Expansion In (

XI) is

grounded to indicate an operation in the single device mode.

Expansion In (

XI) is connected to Expansion Out (XO) of the

previous device in the Depth Expansion or Daisy Chain Mode.

OUTPUTS:

FULL FLAG (

FF

FF)

The Full Flag (

FF) will go low, inhibiting further write

operation, when the write pointer is one location less than the

read pointer, indicating that the device is full. If the read

pointer is not moved after Reset (

RS), the Full-Flag (FF) will go

low after 256 writes for IDT7200, 512 writes for the IDT7201A

and 1,024 writes for the IDT7202A.

EMPTY FLAG (

EF

EF)

The Empty Flag (

EF) will go low, inhibiting further read

operations, when the read pointer is equal to the write pointer,

indicating that the device is empty.

EXPANSION OUT/HALF-FULL FLAG (

XO

XO/HF

HF)

This is a dual-purpose output. In the single device mode,

when Expansion In (

XI) is grounded, this output acts as an

indication of a half-full memory.

After half of the memory is filled and at the falling edge of

the next write operation, the Half-Full Flag (

HF) will be set low

and will remain set until the difference between the write

2679 drw 03

30pF*

1.1K

5V

TO

OUTPUT

680

Ω

or equivalent circuit

Figure 1. Output Load

* Includes scope and jig capacitances.

SIGNAL DESCRIPTIONS

INPUTS:

DATA IN (D0 – D8)

Data inputs for 9-bit wide data.

CONTROLS:

RESET (

RS

RS)

Reset is accomplished whenever the Reset (

RS) input is

taken to a low state. During reset, both internal read and write

pointers are set to the first location. A reset is required after

power up before a write operation can take place. Both the

Read Enable (

RR) and Write Enable (W

W) inputs must be in

the high state during the window shown in Figure 2, (i.e.,

tRSS before the rising edge of

RS

RS) and should not change

until tRSR after the rising edge of

RS

RS. Half-Full Flag (HF

HF)

will be reset to high after Reset (

RS

RS).

WRITE ENABLE (

W

W)

A write cycle is initiated on the falling edge of this input if the

Full Flag (

FF) is not set. Data set-up and hold times must be

adhered to with respect to the rising edge of the Write Enable

(

W). Data is stored in the RAM array sequentially and

independently of any on-going read operation.

After half of the memory is filled and at the falling edge of

the next write operation, the Half-Full Flag (

HF) will be set to

low and will remain set until the difference between the write

pointer and read pointer is less than or equal to one half of the

total memory of the device. The Half-Full Flag (

HF) is then

reset by the rising edge of the read operation.

To prevent data overflow, the Full Flag (

FF) will go low,

inhibiting further write operations. Upon the completion of a

valid read operation, the Full Flag (

FF) will go high after tRFF,

allowing a valid write to begin. When the FIFO is full, the

internal write pointer is blocked from

W, so external changes

in

W will not affect the FIFO when it is full.

READ ENABLE (

RR)

A read cycle is initiated on the falling edge of the Read

Enable (

R) provided the Empty Flag (EF) is not set. The data

is accessed on a First-In/First-Out basis, independent of any

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