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IDT7134LA70L48B Datasheet(PDF) 8 Page - Integrated Device Technology |
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IDT7134LA70L48B Datasheet(HTML) 8 Page - Integrated Device Technology |
8 / 9 page 6.04 8 IDT7134SA/LA HIGH-SPEED 4K x 8 DUAL-PORT STATIC RAM MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/ W W W W W CONTROLLED TIMING(1, 5, 8) TIMING WAVEFORM OF WRITE CYCLE NO. 2, CE CE CE CE CE CONTROLLED TIMING(1, 5) NOTES: 1. R/ W or CE must be High during all address transitions. 2. A write occurs during the overlap (tEW or tWP) of a CE =VIL and R/W = VIL. 3. tWR is measured from the earlier of CE or R/W going High to the end-of-write cycle. 4. During this period, the I/O pins are in the output state, and input signals must not be applied. 5. If the CE Low transition occurs simultaneously with or after the R/W Low transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal ( CE or R/W )is asserted last. 7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured + 500mV from steady state with the Output Test Load (Figure 2). 8. If OE is Low during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the bus for the required tDW. If OE is High during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. 2720 drw 12 R/ W tWC ADDRESS DATAIN CE 1.20 in tDW tWR(3) tDH tEW(2) tAW tAS(6) CE 2720 drw 11 tAW tAS(6) tDW DATAIN ADDRESS tWC R/ W tWP tDH DATAOUT tWZ (7) (4) (4) (2) tOW OE (7) tHZ tLZ (7) tHZ tWR(3) |
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