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IDT74FCT16543ET Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT74FCT16543ET Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 8 page Integrated Device Technology, Inc. MILITARY AND COMMERCIAL TEMPERATURE RANGES SEPTEMBER 1996 ©1996 Integrated Device Technology, Inc. 5.12 DSC-2618/7 1 The IDT logo is a registered trademark of Integrated Device Technology, Inc. FAST CMOS 16-BIT LATCHED TRANSCEIVER FEATURES: • Common features: – 0.5 MICRON CMOS Technology – High-speed, low-power CMOS replacement for ABT functions – Typical tSK(o) (Output Skew) < 250ps – Low input and output leakage ≤1µA (max.) – ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) – Packages include 25 mil pitch SSOP, 19.6 mil pitch TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack – Extended commercial range of -40 °C to +85°C –VCC = 5V ±10% • Features for FCT16543T/AT/CT/ET: – High drive outputs (-32mA IOH, 64mA IOL) – Power off disable outputs permit “live insertion” – Typical VOLP (Output Ground Bounce) < 1.0V at VCC = 5V, TA = 25 °C • Features for FCT162543T/AT/CT/ET: – Balanced Output Drivers: ±24mA (commercial), ±16mA (military) – Reduced system switching noise – Typical VOLP (Output Ground Bounce) < 0.6V at VCC = 5V,TA = 25 °C IDT54/74FCT16543T/AT/CT/ET IDT54/74FCT162543T/AT/CT/ET FUNCTIONAL BLOCK DIAGRAM D C D C 1 B1 1 OEBA 1 CEBA 1 LEBA 1 OEAB 1 CEAB 1 A1 1 LEAB TO 7 OTHER CHANNELS 2618 drw 01 2 OEBA 2 CEBA 2 LEBA D C 2 OEAB 2 CEAB 2 A1 2 B1 2 LEAB TO 7 OTHER CHANNELS 2618 drw 02 D C DESCRIPTION: The FCT16543T/AT/CT/ET and FCT162543T/AT/CT/ET 16-bit latched transceivers are built using advanced dual metal CMOS technology. These high-speed, low-power devices are organized as two independent 8-bit D-type latched transceiv- ers with separate input and output control to permit indepen- dent control of data flow in either direction. For example, the A- to-B Enable (x CEAB) must be LOW in order to enter data from the A port or to output data from the B port. x LEAB controls the latch function. When x LEAB is LOW, the latches are transpar- ent. A subsequent LOW-to-HIGH transition of x LEAB signal puts the A latches in the storage mode. x OEAB performs output enable function on the B port. Data flow from the B port to the A port is similar but requires using x CEBA, xLEBA, and xOEBA inputs. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin. The FCT16543T/AT/CT/ET are ideally suited for driving high-capacitance loads and low-impedance backplanes. The output buffers are designed with power off disable capability to allow "live insertion" of boards when used as backplane drivers. The FCT162543T/AT/CT/ET have balanced output drive with current limiting resistors. This offers low ground bounce, minimal undershoot, and controlled output fall times–reducing the need for external series terminating resistors. The FCT162543T/AT/CT/ET are plug-in replacements for the FCT16543T/AT/CT/ET and 54/74ABT16543 for on-board bus interface applications. |
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