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IDT54FCT164245T Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT54FCT164245T Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 9 page ©1996 IIntegrated Device Technology, Inc. 8.16 DSC-2555/4 Integrated Device Technology, Inc. The IDT logo is a registered trademark of Integrated Device Technology, Inc. IDT54/74FCT164245T FAST CMOS 16-BIT BIDIRECTIONAL 3.3V TO 5V TRANSLATOR 1 DIR 1 OE 1 A1 1 A2 1 A3 1 A4 1 A5 1 A6 1 A7 1 A8 1 B1 1 B2 1 B3 1 B4 1 B5 1 B6 1 B7 1 B8 2555 drw 01 2 DIR 2 OE 2 A1 2 A2 2 A3 2 A4 2 A5 2 A6 2 A7 2 A8 2 B1 2 B2 2 B3 2 B4 2 B5 2 B6 2 B7 2 B8 2555 drw 02 1 MILITARY AND COMMERCIAL TEMPERATURE RANGES FEBRUARY 1996 FEATURES: • 0.5 MICRON CMOS Technology • Bidirectional interface between 3.3V and 5V busses • Control inputs can be driven from either 3.3V or 5V circuits • ESD >2000V per MIL-STD-883, Method 3015; >200V using machine model (C = 200pF, R = 0) • 25 MIL Center SSOP and Cerpack Packages • Extended commercial range of -40 °C to +85°C •VCC1 = 5V ±10%, VCC2 = 2.7V to 3.6V • High drive outputs (-32mA IOH, 64mA IOL) on 5V port • Power-off disable on both ports permits "live insertion" • Typical VOLP (Output Ground Bounce) < 0.9V at VCC1 = 5V, VCC2 = 3.3V, TA = 25 °C DESCRIPTION: The FCT164245T 16-bit 3.3V-to-5V translator is built using advanced dual metal CMOS technology. This high- speed, low-power transceiver is designed to interface be- tween a 3.3V bus and a 5V bus in a mixed 3.3V/5V supply environment. This enables system designers to interface TTL compatible 3.3V components with 5V components. The direction and output enable controls operate these devices as either two independent 8-bit transceivers or one 16-bit trans- ceiver. The A port interfaces with the 3.3V bus; the B port interfaces with the 5V bus. The direction control (xDIR) pin controls the direction of data flow. The output enable (x OE) overrides the direction control and disables both ports. These control signals can be driven from either 3.3V or 5V devices. The FCT164245T is ideally suited for driving high capaci- tance loads and low impedance backplanes. The output buffers are designed with Power-Off Disable capability to allow "hot insertion" of boards when used as backplane drivers. They also allow interface between a mixed supply system and external 5V peripherals. FUNCTIONAL BLOCK DIAGRAM |
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