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IDT7210L40FB Datasheet(PDF) 4 Page - Integrated Device Technology |
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IDT7210L40FB Datasheet(HTML) 4 Page - Integrated Device Technology |
4 / 10 page 11.2 4 IDT7210L 16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR MILITARY AND COMMERCIAL TEMPERATURE RANGES PRELOAD TRUTH TABLE PREL TSX TSM TSL XTP MSP LSP 00 00 Q Q Q 00 01 Q Q Hi Z 00 10 Q Hi Z Q 0 0 1 1 Q Hi Z Hi Z 01 00 Hi Z Q Q 0 1 0 1 Hi Z Q Hi Z 0 1 1 0 Hi Z Hi Z Q 0 1 1 1 Hi Z Hi Z Hi Z 1 0 0 0 Hi Z Hi Z Hi Z 1 0 0 1 Hi Z Hi Z PL 1 0 1 0 Hi Z PL Hi Z 10 11 Hi Z PL PL 1 1 0 0 PL Hi Z Hi Z 1 1 0 1 PL Hi Z PL 1 1 1 0 PL PL Hi Z 1 1 1 1 PL PL PL NOTES: 2577 tbl 02 Hi Z = Output buffers at high impedance (output disabled) Q = Output buffers at low impedance. Contents of output register will be transferred to output pins. PL = Output buffers at high impedance or output disabled. Preload data supplied externally at output pins will be loaded into the output register at the rising edge of CLKP. NOTES ON TWO'S COMPLEMENT FORMATS 1. In two's complement notation, the location of the binary point that signifies the separation of the fractional and integer fileds is just after the sign, between the sign bit (-2 °) and the next significant bit for the multiplier inputs. This same format is carried over to the output format, except that the extended significance of the integer filed is provided to extend the utility of the accumulator. In the case of the output rotation, the output binary point is located between the2 ° and 21 bit positions. The location of the binary point is arbitrary, as long as there is consistency with both the input and output formats. The number filed can be considered entirely integer with the binary point just to the right of the least significant bit for the input, product and the accumulated sum. 2. When in the non-accumulating mode, the first four bits (P34 to P31) will all indicate the sign of the product. Additionally, the P30 term will also indicate the sign with one exception, when multiplying -1 x -1. With the additional bits that are available in this multiplier, the –1 x –1 is a valid operation that yields a +1 product. 3. In operations that require the accumulation of single prod- ucts or sum of products, there is no change in format. To allow for a valid summation beyond that available for a single multiplication product, three additional significant bits (guard bits) are provided. This is the same as if the product was accumulated off-chip in a separate 35-bit wide adder. Taking the sign at the most significant bit position will guarantee that the largest number field will be used. When the accumulated sum only occupies the right hand portion of the accumulator, the sign will be extended into the lesser significant bit positions. ABSOLUTE MAXIMUM RATINGS (1) Symbol Rating Commercial Military Unit VCC Power Supply Voltage -0.5 to +7.0 -0.5 to +7.0 V VTERM Terminal Voltage with Respect to GND –0.5 to VCC +0.5V –0.5 to VCC +0.5V V TA Operating Temperature 0 to +70 –55 to +125 °C TBIAS Temperature Under Bias –55 to +125 –65 to +135 °C TSTG Storage Temperature –55 to +125 –65 to +150 °C IOUT DC Output Current 50 50 mA NOTE: 2577 tbl 03 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating condi- tions for extended periods may affect reliability. CAPACITANCE (TA = +25 °C, f = 1.0MHz) Symbol Parameter(1) Conditions Max. Unit CIN Input Capacitance VIN = 0V 10 pF COUT Output Capacitance VOUT = 0V 12 pF NOTE: 2577 tbl 04 1. This parameter is measured at characterization and not 100%tested. |
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