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IDT72841L10TF Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT72841L10TF Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 16 page SyncFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc. 2001 Integrated Device Technology, Inc. DSC-3034/1 APRIL 2001 DUAL CMOS SyncFIFO™ DUAL 256 x 9, DUAL 512 x 9, DUAL 1,024 x 9, DUAL 2,048 x 9, DUAL 4,096 x 9, DUAL 8,192 x 9 IDT72801 IDT72811 IDT72821 IDT72831 IDT72841 IDT72851 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE .EATURES: ••••• The IDT72801 is equivalent to two IDT72201 256 x 9 FIFOs ••••• The IDT72811 is equivalent to two IDT72211 512 x 9 FIFOs ••••• The IDT72821 is equivalent to two IDT72221 1,024 x 9 FIFOs ••••• The IDT72831 is equivalent to two IDT72231 2,048 x 9 FIFOs ••••• The IDT72841 is equivalent to two IDT72241 4,096 x 9 FIFOs ••••• The IDT72851 is equivalent to two IDT72251 8,192 x 9 FIFOs ••••• Offers optimal combination of large capacity, high speed, design flexibility and small footprint ••••• Ideal for prioritization, bidirectional, and width expansion applications ••••• 10 ns read/write cycle time for the IDT72801/72811/72821/72831/ 72841 (excluding the IDT72851) ••••• 15 ns read/write cycle time for the IDT72851 ••••• Separate control lines and data lines for each FIFO ••••• Separate Empty, Full, Programmable Almost-Empty and Almost- Full flags for each FIFO ••••• Enable puts output data lines in high-impedance state ••••• Space-saving 64-pin Thin Quad Flat Pack (TQFP) and Slim Thin Quad Flatpack (STQFP) • Industrial temperature range (–40 °°°°°C to +85°°°°°C) is available DESCRIPTION: The IDT72801/72811/72821/72831/72841/72851 are dual synchronous (clocked)FIFOs. ThedeviceisfunctionallyequivalenttotwoIDT72201/72211/ 72221/72231/72241/72251 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs (designated FIFO A and FIFO B) contained in the IDT72801/72811/72821/72831/72841/72851 has a 9-bit input data port (DA0 - DA8, DB0 - DB8) and a 9-bit output data port (QA0 - QA8, QB0 - QB8). Each inputportiscontrolledbyafree-runningclock(WCLKA,WCLKB),andtwoWrite Enable pins ( WENA1,WENA2,WENB1,WENB2). Dataiswrittenintoeachof the two arrays on every rising clock edge of the Write Clock (WCLKA, WCLKB) when the appropriate write enable pins are asserted. The output port of each FIFO bank is controlled by its associated clock pin (RCLKA, RCLKB) and two Read Enable pins ( RENA1, RENA2, RENB1, RENB2).TheReadClockcanbetiedtotheWriteClockforsingleclockoperation orthetwoclockscanrunasynchronousofoneanotherfordualclockoperation. An Output Enable pin ( OEA, OEB) is provided on the read port of each FIFO for three-state output control. Each of the two FIFOs has two fixed flags, Empty ( EFA,EFB)andFull(FFA, FFB). Twoprogrammableflags,Almost-Empty(PAEA,PAEB)andAlmost-Full ( PAFA,PAFB),areprovidedforeachFIFObanktoimprovememoryutilization. If not programmed, the programmable flags default to empty+7 for PAEAand PAEB, and full-7 for PAFA and PAFB. TheIDT72801/72811/72821/72831/72841/72851architecturelendsitself to many flexible configurations such as: • 2-level priority data buffering • Bidirectional operation • Width expansion • Depth expansion These FIFOs is fabricated using IDT's high-performance submicron CMOS technology. .UNCTIONAL BLOCK DIAGRAM WCLKA WENA1 WENA2 DA0 - DA8 LDA OFFSET REGISTER INPUT REGISTER RAM ARRAY 256 x 9, 512 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9 WRITE CONTROL LOGIC WRITE POINTER RESET LOGIC OUTPUT REGISTER OEA RSA QA0 - QA8 RCLKA RENA1 RENA2 READ CONTROL LOGIC READ POINTER FLAG LOGIC EFA PAEA PAFA FFA 3034 drw 01 WCLKB WENB1 WENB2 DB0 - DB8 LDB OFFSET REGISTER INPUT REGISTER WRITE CONTROL LOGIC WRITE POINTER RESET LOGIC OUTPUT REGISTER OEB RSB QB0 - QB8 RCLKB RENB1 RENB2 READ CONTROL LOGIC READ POINTER FLAG LOGIC EFB PAEB PAFB FFB RAM ARRAY 256 x 9, 512 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9 |
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