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IDT72261L12PFB Datasheet(PDF) 3 Page - Integrated Device Technology |
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IDT72261L12PFB Datasheet(HTML) 3 Page - Integrated Device Technology |
3 / 30 page 3 IDT72261/72271 SyncFIFO ™ 16,384 x 9, 32,768 x 9 MILITARY AND COMMERCIAL TEMPERATURE RANGES The Retransmit function allows the read pointer to be reset to the first location in the RAM array. It is synchronized to RCLK when RT is LOW. This feature is convenient for sending the same data more than once. If, at any time, the FIFO is not actively performing a function, the chip will automatically power down. This occurs if neither a read nor a write occurs within 10 cycles of the faster clock, RCLK or WCLK. During the Power Down state, supply current consumption (ICC2) is at a minimum. Initiating any operation (by activating control inputs) will immediately take the device out of the Power Down state. The IDT72261/72271 are depth expandable. The addition of external components is unnecessary. The IR and OR functions, together with REN and WEN, are used to extend the total FIFO memory capacity. The FS line ensures optimal data flow through the FIFO. It is tied to GND if the RCLK frequency is higher than the WCLK frequency or to Vcc if the RCLK frequency is lower than the WCLK frequency The IDT72261/72271 is fabricated using IDT’s high speed submicron CMOS technology. NOTES : 1. DNC = Do not connect. 2. This pin may either be tied to ground or left open. PGA (G68-1, order code: G) TOP VIEW PIN CONFIGURATIONS (CONT.) D8 Pin 1 Designator AB C D E F G H J K L Q0 D2 PAF DNC RCLK REN OE VCC DNC MRS LD WCLK PRS VCC WEN VCC D7 D6 PAE D4 D3 D1 D0 Q1 Q2 Q3 Q4 Q8 Q7 DNC DNC VCC DNC DNC DNC DNC DNC DNC DNC HF EF/ OR FF/ IR 11 10 09 08 07 06 05 04 03 02 01 RT FWFT/ SI D5 VCC DNC Q6 Q5 3036 drw 03 SEN FS GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND (2) (2) (2) (2) (2) (2) (2) (2) (2) |
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