11.2

3

IDT7210L

16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR

MILITARY AND COMMERCIAL TEMPERATURE RANGES

NC

RND

TC

TSX

NC

NC

NC

11

10

09

08

07

06

05

04

03

02

01

ABC

D

E

F

G

H

J

KL

Pin 1

Designator

G68-2

2577 drw 05

ACC

TSL

SUB

TSM

GND

PGA

TOP VIEW

PIN DESCRIPTIONS

2577 tbl 01

Pin Name

I/O

Description

I

Data Inputs

I/O

are LSP register outputs - enabled by TSL.

I/O

MSP register outputs - enabled by TSM. MSP register can be preloaded when PREL = 1.

I/O

XTP register outputs - enabled by TSX. XTP register can be preloaded through these inputs when

PREL = 1.

CLKX

I

CLKY

I

CLKP

I

Output data loaded into output register on rising edge of CLKP.

TSX

I

TSM

I

TSL

I

PREL

I

ACC

I

This input is loaded into the control register on the rising edge of (CLKX + CLKY).

When ACC = 1 and SUB = 0 an accumulate operation is performed. When ACC = 1 and SUB = 1, a

subtract operation is performed. When ACC = 0, the SUB input is a don't care and the device acts as a

simple multipler with no accumulation

SUB

I

This input is loaded into the control register on the rising edge of (CLKX + CLKY).

This input is active only when ACC = 1. When SUB = 1 the contents of the output register are subtracted

from the result and stored back in the output register. When SUB = 0 the contents of the output register

are added to the result and stored back in the output register

TC

I

This input is loaded into the control register on the rising edge of (CLKX + CLKY).

When TC = 1, the X and Y input are assumed to be in two's complement form. When TC = 0, X and Y

inputs are assumed to be in unsigned magnitude form

RND

I

This input is loaded into the control register on the rising edge of (CLKX + CLKY).

RND is inactive when low. RND = 1, adds a "1" to the most significant bit of the LSP, to round MSP and

XTP data