IDT72261L12GB datasheet(11/30 Pages) IDT

Part #	IDT72261L12GB

Description	CMOS SUPERSYNC FIFOO 16,384 x 9, 32,768 x 9

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Manufacturer	IDT [Integrated Device Technology]

Direct Link	http://www.idt.com

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IDT72261/72271 SyncFIFO

™

16,384 x 9, 32,768 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Figure 3. Offset Register Location and Default Values

The

IR status not only measures the contents of the FIFO

memory, but also counts the presence of a word in the output

register. Thus, in FWFT mode, the total number of writes

necessary to deassert

IR is one greater than needed to assert

FF in IDT Standard mode.

FF/IR is synchronized to WCLK. It is double-registered to

enhance metastable immunity.

EMPTY FLAG (

EF

EF/OR

OR)

This is a dual purpose pin. In the IDT Standard Mode, the

Empty Flag (

EF) function is selected. When the FIFO is empty

(i.e. the read pointer catches up to the write pointer),

EF will go

LOW, inhibiting further read operations. When

EF is HIGH,

the FIFO is not empty.

When writing the first word to an empty FIFO, the deassertion

time of

EF is variable, and can be represent by the First Word

Latency parameter, tFWL1, which is measured from the rising

WCLK edge that writes the first word to the rising RCLK edge

that updates the flag. tFWL1 includes any delays due to clock

skew and can be expressed as follows:

tFWL1 max. = 10*Tf + 2*TRCLK (in ns)

where Tf is either the RCLK or the WCLK period, whichever

is shorter, and TRCLK is the RCLK period. Since no read can

take place until

EF goes HIGH, the tFWL1 delay determines

how early the first word can be available at Qn. This delay has

no effect on the reading of subsequent words.

equal to or less than the cycle period of the non-selected

clock.

The selected clock must be continuous. It is, however,

permissible to stop the non-selected clock. Note, so long as

RCLK is idle,

EF/OR and PAE will not be updated. Likewise,

as long as WCLK is idle,

FF/IR and PAF will not be updated.

Changing the FS setting during FIFO operation (i.e. read-

ing or writing) is not permitted; however, such a change at the

time of Master Reset or Partial Reset is all right. FS is an

asynchronous input.

OUTPUTS:

FULL FLAG (

FF

FF/IR

IR)

This is a dual purpose pin. In IDT Standard Mode, the Full

Flag (

FF) function is selected. When the FIFO is full (i.e. the

write pointer catches up to the read pointer),

FF will go LOW,

inhibiting further write operation. When

FF is HIGH, the FIFO

is not full. If no reads are performed after a reset (either

MRS

or

PRS), FF will go LOW after 16,384 writes tor the IDT72261

and 32,768 writes to the IDT72271.

In FWFT Mode, the Input Ready (

IR) function is selected. IR

goes LOW when memory space is available for writing in

data. When there is no longer any free space left,

IR goes

HIGH, inhibiting further write operation.

If no reads are

performed after a reset (either

MRS or PRS), IR will go HIGH

after 16,385 writes for the IDT72261 and 32,769 writes for the

IDT72271.

NOTE:

1. Any bits of the offset register not being programmed should be set to zero.

EMPTY OFFSET (LSB) REG.

87

0

EMPTY OFFSET (MSB) REG.

00H

8

5

0

3036 drw 05

72261 – 16,384 x 9–BIT

FULL OFFSET (LSB) REG.

87

0

FULL OFFSET (MSB) REG.

00H

8

5

0

DEFAULT VALUE

07FH if

LD is LOW at Master Reset

3FFH if

LD is HIGH at Master Reset

DEFAULT VALUE

07FH if

LD is LOW at Master Reset

3FFH if

LD is HIGH at Master Reset

EMPTY OFFSET (LSB) REG.

DEFAULT VALUE

07FH if

LD is LOW at Master Reset

3FFH if

LD is HIGH at Master Reset

87

0

EMPTY OFFSET (MSB) REG.

00H

8

6

0

3036 drw 06

72271 – 32,768 x 9–BIT

FULL OFFSET (LSB) REG.

87

0

FULL OFFSET (MSB) REG.

00H

8

6

0

DEFAULT VALUE

07FH if

LD is LOW at Master Reset

3FFH if

LD is HIGH at Master Reset

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IDT72261L12GB Datasheet(PDF) 11 Page - Integrated Device Technology

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