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IDT7210L40CB Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT7210L40CB Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 10 page Integrated Device Technology, Inc. MILITARY AND COMMERCIAL TEMPERATURE RANGES AUGUST 1995 ©1995 Integrated Device Technology, Inc. 11.2 DSC-2018/7 IDT7210L 16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR FEATURES: • 16 x 16 parallel multiplier-accumulator with selectable accumulation and subtraction • High-speed: 20ns multiply-accumulate time • IDT7210 features selectable accumulation, subtraction, rounding and preloading with 35-bit result • IDT7210 is pin and function compatible with the TRW TDC1010J, TMC2210, Cypress CY7C510, and AMD AM29510 • Performs subtraction and double precision addition and multiplication • Produced using advanced CMOS high-performance technology • TTL-compatible • Available in topbraze DIP, PLCC, Flatpack and Pin Grid Array • Military product compliant to MIL-STD-883, Class B • Standard Military Drawing #5962-88733 is listed on this function • Speeds available: Commercial: L20/25/35/45/55/65 Military: L25/30/40/55/65/75 DESCRIPTION: The IDT7210 is a high-speed, low-power 16 x 16-bit parallel multiplier-accumulator that is ideally suited for real-time digital signal processing applications. Fabricated using CMOS silicon gate technology, this device offers a very low-power alternative to existing bipolar and NMOS counterparts, with only 1/7 to 1/10 the power dissipation and exceptional speed (25ns maximum) performance. A pin and functional replacement for TRW’s TDC1010J the IDT7210 operates from a single 5 volt supply and is compatible with standard TTL logic levels. The architecture of the IDT7210 is fairly straightforward, featuring individual input and output registers with clocked D-type flip-flop, a preload capability which enables input data to be preloaded into the output registers, individual three-state output ports for the Extended Product (XTP) and Most Significant Product (MSP) and a Least Significant Product output (LSP) which is multiplexed with the Y input. The XIN and YIN data input registers may be specified through the use of the Two’s Complement input (TC) as either a two’s complement or an unsigned magnitude, yielding a full- precision 32-bit result that may be accumulated to a full 35-bit result. The three output registers – Extended Product (XTP), Most Most Significant Product (MSP) and Least Significant Product (LSP) – are controlled by the respective TSX, TSM and TSL input lines. The LSP output can be routed through YIN ports. FUNCTIONAL BLOCK DIAGRAM 1 MULTIPLIER ARRAY ACCUMULATOR MSP REGISTER LSP REGISTER XTP REGISTER 16 TSL 16 XTPOUT (P34-P32) 3 3 35 +/– TSX PREL CLKP 35 32 YREGISTER REGISTER XREGISTER CONTROL 16 416 CLKX CLKY RND, TC ACC, SUB, XIN (X15-X0) YIN (Y15-Y0/P15-P0) TSM MSPOUT (P31-P16) IDT7210 2577 drw 01 PREL + |
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