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IDT72815LB10BG Datasheet(PDF) 2 Page - Integrated Device Technology |
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IDT72815LB10BG Datasheet(HTML) 2 Page - Integrated Device Technology |
2 / 26 page COMMERCIALANDINDUSTRIAL TEMPERATURERANGES IDT72805LB/72815LB/72825LB/72835LB/72845LB CMOS Dual SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 2 PIN CONFIGURATIONS WCLKA DA3 DA1 DA0 DB13 DB16 RCLKB LDB RSB QB17 QB16 PAFA DA4 WENA DA2 DB12 DB15 RENB OEB EFB QB15 QB14 FFA RXIA WXIA DA5 DB14 DB11 GND DB17 GND QB13 QB11 QB8 QB10 QB12 VCC DB7 DB10 DB8 FLA QA2 QA0 RXOA QA1 QA4 QA3 WXOA/ HFA PAEA DB9 DB6 VCC VCC QB9 QB7 QA5 QA6 GND VCC GND GND GND VCC GND QB6 QB5 QA7 QA9 VCC VCC DA6 DA9 PAEB WXOB/ HFB QB3 QB4 QB1 QA8 QA10 QA12 VCC DA7 DA10 DA8 FLB QB2 QB0 RXOB QA11 QA13 GND DA17 GND DA11 DA14 DB5 WXIB RXIB FFB QA14 QA15 EFA OEA RENA DA15 DA12 DB2 WENB DB4 PAFB QA16 QA17 RSA LDA RCKLA DA16 DA13 DB0 DB1 DB3 WCLKB 123 456 789 10 11 A B C D E F G H J K L PIN 1 3139 drw 02 PBGA (BG121-1, order code: BG) TOP VIEW NOTE: 1. The PBGA is only available for the IDT72805LB/72815LB/72825LB in the 15 or 25 ns speed grade. IDT72205LB/72215LB/72225LB/72235LB/72245LB FIFOs in a single package with all associated control, data, and flag lines assigned to independent pins. These devices are very high-speed, low-power First-In, First-Out (FIFO) memories with clocked read and write controls. These FIFOs are applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs contained in these devices has an 18-bit input and output port. Each input port is controlled by a free-running clock (WCLK), and an input enable pin ( WEN). Data is read into the synchronous FIFO on every clock when WEN is asserted. The output port of each FIFO bank is controlled by another clock pin (RCLK) and another enable pin ( REN). The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation. An Output Enable pin ( OE) is provided on the read port of each FIFO for three-state control of the output. The synchronous FIFOs have two fixed flags, Empty Flag/Output Ready ( EF/OR) and Full Flag/Input Ready (FF/IR), and two programmable flags, Almost-Empty( PAE)andAlmost-Full(PAF).Theoffsetloadingoftheprogram- mable flags is controlled by a simple state machine, and is initiated by asserting the Load pin ( LD). A Half-Full flag (HF) is available for each FIFO that is implemented as a single device configuration. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through (FWFT) mode. In IDT Standard Mode, the first word written to an empty FIFO will not appear on the data output lines unless a specific read operation is performed. A read operation, which consists of activating REN and enabling a rising RCLK edge, will shift the word from internal memory to the data output lines. In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three transitions of the RCLK signal. A REN does not have to be asserted for accessing the first word. These devices are depth expandable using a daisy-chain technique or First Word Fall Through (FWFT) mode. The XI and XO pins are used to expand the FIFOs. In depth expansion configuration, FLisgroundedonthefirstdeviceand set to HIGH for all other devices in the Daisy Chain. The IDT72805LB/72815LB/72825LB/72835LB/72845LB are fabricated using IDT’s high-speed submicron CMOS technology. DESCRIPTION (Continued) |
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