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IDT6167LA85YB Datasheet(PDF) 7 Page - Integrated Device Technology |
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IDT6167LA85YB Datasheet(HTML) 7 Page - Integrated Device Technology |
7 / 8 page 5.2 7 IDT6167SA/LA CMOS STATIC RAM 16K (16K x 1-BIT) MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING WAVEFORM OF WRITE CYCLE NO. 1, ( WE WE CONTROLLED TIMING)(1, 2, 4) TIMING WAVEFORM OF WRITE CYCLE NO. 2, ( CS CS CONTROLLED TIMING)(1, 2, 4) NOTES: 1. WE or CS must be inactive during all address transitions. 2. A write occurs during the overlap of a LOW CS and a LOW WE. 3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle. 4. If the CS low transition occurs simultaneously with or after the WE LOW transition, the outputs remain in the high-impedance state. 5. Transition is measured ±200mV from steady state. 6. During this period, the I/O pins are in the output state and the input signals must not be applied. CS 2981 drw 08 tAW tWR tDW DATAIN ADDRESS tWC WE tWP tDH DATAOUT tOW tAS DATAIN VALID (5) PREVIOUS DATAOUT VALID (6) DATAOUT VALID (6) (3) tWHZ (5) tCHZ (5) t CS 2981 drw 09 tAW tDW DATAIN ADDRESS tWC WE tCW tDH tAS tWR DATAIN VALID (3) |
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