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IDT72521L35J Datasheet(PDF) 8 Page - Integrated Device Technology |
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IDT72521L35J Datasheet(HTML) 8 Page - Integrated Device Technology |
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8 / 28 page  5.32 8 IDT72511/IDT72521 BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY MILITARY AND COMMERCIAL TEMPERATURE RANGES request DMA circuitry can also be reset independently. A software Reset All command resets all the pointers, the DMA request circuitry, and sets all the Configuration Registers to their default condition. Note that a hardware reset is NOT the same as a software Reset All command. Table 6 shows the BiFIFO state after the different hardware and software resets Status Register The Status Register reports the state of the programmable flags and the DMA read/write direction. The Status Register is read by setting CSA = 0, A1 = 1, A0 = 1 (see Table 1). See Table 7 for the Status Register format. Configuration Registers The eight Configuration Register formats are shown in RESET COMMAND FUNCTIONS 2668 tbl 04 Table 3. Reset Command Functions DMA DIRECTION COMMAND FUNCTIONS Operands Function XX0 Write B →A FIFO XX1 Read A →B FIFO Reset Operands Function 000 No Operation 001 Reset B →A FIFO (Read, Write, and Rewrite Pointers = 0) 010 Reset A →B FIFO (Read, Write, and Reread Pointers = 0) 011 Reset B →A and A→B FIFO 100 Reset Internal DMA Request Circuitry 101 No Operation 110 No Operation 111 Reset All Reset The IDT72511 and IDT72521 have a hardware reset pin ( RS) that resets all BiFIFO functions. A hardware reset re- quires the following four conditions: RBandWBmustbeHIGH, RER and REW must be HIGH, LDRER and LDREW must be LOW, and DSA must be HIGH (Figure 9). After a hardware reset, the BiFIFO is in the following state: Configuration Registers 0-3 are 0000H, Configuration Register 4 is set to 6420H, and Configuration Registers 5, 6 and 7 are 0000H. Additionally, all the pointers including the Reread and Rewrite Pointers are set to 0, the DMA direction is set to B →A write, and the internal DMA request circuitry is cleared (set to its initial state). A software reset command can reset A →B pointers and the B →A pointers to 0 independently or together. The internal CS CSA A1 A0 Read Write 00 0 B →A FIFO A →B FIFO 0 0 1 9-bit Bypass Path 9-bit Bypass Path 0 1 0 Configuration Registers Configuration Registers 0 1 1 Status Register Command Register 1 X X Disabled Disabled PORT A RESOURCE SELECTION 2668 tbl 03 Table 1. Accessing Port A Resources Using CSA, A0 and A1 Command Opcode Function 0000 Reset BiFIFO (see Table 3) 0001 Select Configuration Register (see Table 4) 0010 Load Reread Pointer with Read Pointer Value 0011 Load Rewrite Pointer with Write Pointer Value 0100 Load Read Pointer with Reread Pointer Value 0101 Load Write Pointer with Rewrite Pointer Value 0110 Set DMA Transfer Direction (see Table 5) 0111 Reserved 1000 Increment A →B FIFO Read Pointer (Port B) 1001 Increment B →A FIFO Write Pointer (Port B) 1010 Reserved 1011 Reserved COMMAND OPERATIONS 2668 tbl 07 Table 5. Set DMA Direction Command Functions. Command Only Operates in Peripheral Interface Mode Operands Function 000 Select Configuration Register 0 001 Select Configuration Register 1 010 Select Configuration Register 2 011 Select Configuration Register 3 100 Select Configuration Register 4 101 Select Configuration Register 5 110 Select Configuration Register 6 111 Select Configuration Register 7 SELECT CONFIGURATION REGISTER/ COMMAND FUNCTIONS 2668 tbl 06 Table 4. Select Configuration Register Functions. 2668 tbl 05 Table 2. Functions Performed by Port A Commands |
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