IDT723641L30PQF datasheet(2/23 Pages) IDT

Part #	IDT723641L30PQF

Description	CMOS SyncFIFOO 512 x 36, 1024 x 36, 2048 x 36

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Manufacturer	IDT [Integrated Device Technology]

Direct Link	http://www.idt.com

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IDT723631/723641/723651 CMOS SyncFIFO

™

512 x 36, 1024 x 36, 2048 x 36

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DESCRIPTION (CONTINUED)

stored in memory. Communication between each port may

take place with two 36-bit mailbox registers. Each mailbox

register has a flag to signal when new mail has been stored.

Two or more devices may be used in parallel to create wider

data paths. Expansion is also possible in word depth.

The IDT723631/723641/723651 is a clocked FIFO, which

means each port employs a synchronous interface. All data

transfers through a port are gated to the LOW-to-HIGH

transition of a continuous (free-running) port clock by enable

signals. The continuous clocks for each port are independent

PIN CONFIGURATION

of one another and can be asynchronous or coincident. The

enables for each port are arranged to provide a simple

interface between microprocessors and/or buses with syn-

chronous control.

The input-ready (IR) flag and almost-full (

AF) flag of the

FIFO are two-stage synchronized to CLKA. The output-ready

(OR) flag and almost-empty (

AE) flag of the FIFO are two-

stage synchronized to CLKB. Offset values for the almost-full

and almost empty flags of the FIFO can be programmed from

port A or through a serial input.

*

NC

A35

A34

A33

A32

VCC

A31

A30

GND

A29

A28

A27

A26

A25

A24

A23

GND

A22

VCC

A21

A20

A19

A18

GND

A17

A16

A15

A14

A13

VCC

A12

NC

B35

B34

B33

B32

GND

B31

B30

B29

B28

B27

B26

VCC

B25

B24

GND

B23

B22

B21

B20

B19

B18

GND

B17

B16

VCC

B15

B14

B13

B12

GND

NC

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3023 drw 02

*Electrical pin 1 in center of beveled edge. Pin 1 identifier in corner.

Notes:

1.

NC – No internal connection

2.

Uses Yamaichi socket IC51-1324-828

PQFP (PQ132-1, order code: PQF)

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