IDT72V02L25J datasheet(9/13 Pages) IDT

Part #	IDT72V02L25J

Description	3.3 VOLT CMOS ASYNCHRONOUS FIFO 512 x 9, 1024 x 9, 2048 x 9, 4096 x 9

Download	13 Pages

Scroll/Zoom	100%

Manufacturer	IDT [Integrated Device Technology]

Direct Link	http://www.idt.com

Logo

9 / 13 page

5.08

9

IDT72V01/72V02/72V03/72V04 3.3 VOLT CMOS ASYNCHRONOUS FIFO

512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9

COMMERCIAL TEMPERATURE RANGE

W

XI

R

2679 drw 13

WRITE TO

FIRST PHYSICAL

LOCATION

READ FROM

FIRST PHYSICAL

LOCATION

t XIS

t XIR

t XI

t XIS

Figure 11. Expansion In

OPERATING MODES:

Care must be taken to assure that the appropriate flag is

monitored by each system (i.e.

FF is monitored on the device

where

Wisused;EFismonitoredonthedevicewhereRisused).

For additional information, refer to Tech Note 8:

Operating

FIFOs on Full and Empty Boundary Conditions and Tech Note

6:

Designing with FIFOs.

Single Device Mode

A single IDT72V01/72V02/72V03/72V04 may be used

when the application requirements are for 512/1024/2048/

4096 words or less. IDT72V01/72V02/72V03/72V04 is in a

Single Device Configuration when the Expansion In (

XI)

control input is grounded (see Figure 12).

Depth Expansion

The IDT72V01/72V02/72V03/72V04 can easily be adapted

to applications when the requirements are for greater than

512/1,024/2,048/4,096 words. Figure 14 demonstrates Depth

Expansion using three IDT72V01/72V02/72V03/72V04s. Any

depth can be attained by adding additional IDT72V01/72V02/

72V03/72V04s. The IDT72V01/72V02/72V03/72V04 oper-

ates in the Depth Expansion mode when the following condi-

tions are met:

1. The first device must be designated by grounding the First

Load (

FL) control input.

2. All other devices must have

FL in the high state.

3. The Expansion Out (

XO) pin of each device must be tied to

the Expansion In (

XI) pin of the next device. See Figure 14.

4. External logic is needed to generate a composite Full Flag

(

FF) and Empty Flag (EF). This requires the ORing of all

EFs and ORing of all FFs (i.e. all must be set to generate the

correct composite

FF or EF). See Figure 14.

5. The Retransmit (

RT) function and Half-Full Flag (HF) are

not available in the Depth Expansion Mode.

For additional information, refer to Tech Note 9:

Cascading

FIFOs or FIFO Modules.

USAGE MODES:

Width Expansion

Word width may be increased simply by connecting the

corresponding input control signals of multiple devices. Sta-

tus flags (

EF, FF and HF) can be detected from any one device.

Figure 13 demonstrates an 18-bit word width by using two

IDT72V01/72V02/72V03/72V04s. Any word width can be

attained by adding additional IDT72V01/72V02/72V03/72V04s

(Figure 13).

Bidirectional Operation

Applications which require data buffering between two

systems (each system capable of Read and Write operations)

can be achieved by pairing IDT72V01/72V02/72V03/72V04s

as shown in Figure 16. Both Depth Expansion and Width

Expansion may be used in this mode.

Data Flow-Through

Two types of flow-through modes are permitted, a read

flow-through and write flow-through mode. For the read flow-

through mode (Figure 17), the FIFO permits a reading of a

single word after writing one word of data into an empty FIFO.

The data is enabled on the bus in (tWEF + tA) ns after the rising

edge of

W, called the first write edge, and it remains on the

bus until the

R line is raised from low-to-high, after which the

bus would go into a three-state mode after tRHZ ns. The

EF line

would have a pulse showing temporary deassertion and then

would be asserted.

In the write flow-through mode (Figure 18), the FIFO

permits the writing of a single word of data immediately after

reading one word of data from a full FIFO. The

R line causes

the

FF to be deasserted but the W line being low causes it to

be asserted again in anticipation of a new data word. On the

rising edge of

W, the new word is loaded in the FIFO. The W

line must be toggled when

FF is not asserted to write new data

in the FIFO and to increment the write pointer.

Compound Expansion

The two expansion techniques described above can be

applied together in a straightforward manner to achieve large

FIFO arrays (see Figure 15).

Similar Part No. - IDT72V02L25J

Manufacturer	Part #	Datasheet	Description
Integrated Device Techn...	IDT72V02L25J	149Kb / 12P	3.3 VOLT CMOS ASYNCHRONOUS FIFO
Integrated Device Techn...	IDT72V02L25JI	149Kb / 12P	3.3 VOLT CMOS ASYNCHRONOUS FIFO

More results

Similar Description - IDT72V02L25J

Manufacturer	Part #	Datasheet	Description
Integrated Device Techn...	IDT7203	147Kb / 14P	CMOS ASYNCHRONOUS FIFO 2048 x 9, 4096 x 9, 8192 x 9 and 16384 x 9
	IDT72421	196Kb / 14P	CMOS SyncFIFOO 64 X 9, 256 x 9, 512 x 9, 1024 X 9, 2048 X 9 and 4096 x 9
	IDT72201	199Kb / 19P	CMOS SyncFIFO 64 X 9, 256 x 9, 512 x 9, 1024 X 9, 2048 X 9 and 4096 x 9
	IDT7200L	145Kb / 13P	CMOS ASYNCHRONOUS FIFO 256 x 9, 512 x 9, 1,024 x 9
	IDT72103	314Kb / 31P	CMOS PARALLEL-SERIAL FIFO 2048 x 9, 4096 x 9
Sharp Corporation	LH540204	156Kb / 18P	CMOS 4096 x 9 Asynchronous FIFO
Integrated Device Techn...	IDT72131	126Kb / 13P	CMOS PARALLEL-TO-SERIAL FIFO 2048 X 9 4096 X 9
Integrated Device Techn...	IDT7280	142Kb / 12P	CMOS DUAL ASYNCHRONOUS FIFO DUAL 256 x 9, DUAL 512 x 9, DUAL 1024 x 9
List of Unclassifed Man...	IDT7202LA25SOI	313Kb / 14P	CMOS ASYNCHRONOUS FIFO 256 x 9, 512 x 9 and 1,024 x 9
Integrated Device Techn...	IDT7202	144Kb / 14P	CMOS ASYNCHRONOUS FIFO 256 x 9, 512 x 9 and 1,024 x 9

More results

IDT72V02L25J Datasheet(PDF) 9 Page - Integrated Device Technology

IDT72V02L25J Datasheet(HTML) 9 Page - Integrated Device Technology

Similar Part No. - IDT72V02L25J

Similar Description - IDT72V02L25J

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13

Datasheet Download

Link URL