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IDT72361320PQFI Datasheet(PDF) 7 Page - Integrated Device Technology |
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IDT72361320PQFI Datasheet(HTML) 7 Page - Integrated Device Technology |
7 / 26 page 7 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT723613 CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 Figure 1. Typical Characteristics: Supply Current vs Clock Frequency CALCULATING POWER DISSIPATION The ICCf current for the graph in Figure 1 was taken while simultaneously reading and writing the FIFO on the IDT723613 with CLKA and CLKB set to fS. All date inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were disconnected to normalize the graph to a zero-capacitance load. Once the capacitive lead per data-output channel is known, the power dissipation can be calculated with the equation below. With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of the IDT723613 may be calculated by: PT = VCC x ICC(f) + Σ[CL x (VOH – VOL)2 x fo) where: CL = output capacitive load fo = switching frequency of an output VOH = output high-level voltage VOL = output high-level voltage When no reads or writes are occurring on the IDT723613, the power dissipated by a single clock (CLKA or CLKB) input running at frequency fS is calculated by: PT = VCC x fS x 0.29mA/MHz 0 10 20 3040 5060 70 0 50 100 150 200 250 300 350 400 fS Clock Frequency MHz 80 3145 drw04 fdata = 1/2 fS TA = 25 °C CL = 0 pF VCC = 5.5V VCC = 5V VCC = 4.5V |
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