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IDT71V421L25JI Datasheet(PDF) 5 Page - Integrated Device Technology |
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IDT71V421L25JI Datasheet(HTML) 5 Page - Integrated Device Technology |
5 / 14 page 6.42 IDT71V321/71V421S/L High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges 5 Data Retention Waveform VCC CE 3.0V 3.0V DATA RETENTION MODE tCDR tR VIH VIH VDR VDR ≥ 2.0V 3026 drw 04 , AC Test Conditions 590 Ω 30pF 435 Ω DATAOUT 590 Ω 435 Ω 5pF DATAOUT 3026 drw 05 3.3V 3.3V BUSY INT Figure 1. AC Output Test Load Figure 2. Output Test Load (for tHZ, tLZ, tWZ, and tOW) * Including scope and jig. Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 5ns 1.5V 1.5V Figures 1 and 2 3026 tbl 08 AC Electrical Characteristics Over the Operating Temperature Supply Voltage Range(2) 71V321X25 71V421X25 Com 'l & Ind 71V321X35 71V421X35 Com 'l Only 71V321X55 71V421X55 Com 'l Only Unit Sym bol Param eter Min. Max. Min. Max. Min. Max. READ CYCLE tRC Read Cycle Time 25 ____ 35 ____ 55 ____ ns tAA Address Access Time ____ 25 ____ 35 ____ 55 ns tACE Chip Enable Access Time ____ 25 ____ 35 ____ 55 ns tAOE Output Enable Access Time ____ 12 ____ 20 ____ 25 ns tOH Output Hold from Address Change 3 ____ 3 ____ 3 ____ ns tLZ Output Low-Z Time(1,2) 0 ____ 0 ____ 0 ____ ns tHZ Output High-Z Time(1,2) ____ 12 ____ 15 ____ 30 ns tPU Chip Enable to Power Up Time (2) 0 ____ 0 ____ 0 ____ ns tPD Chip Disable to Power Down Time(2) ____ 50 ____ 50 ____ 50 ns 3026 tbl 09 NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. 'X' in part numbers indicates power rating (S or L). |
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