5.01

6

IDT72401, IDT72402, IDT72403, IDT72404

CMOS PARALLEL FIFO 64 x 4-BIT AND 64 x 5-BIT

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING DIAGRAMS (Continued)

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SHIFT OUT

OUTPUT DATA

OUTPUT READY

A-DATA

(1)

(2)

(3)

(4)

(5)

(6)

(7)

B-DATA

A or B

Figure 6. The Mechanism of Shifting Data Out of the FIFO

NOTES:

1. Output Ready HIGH indicates that data is available and a Shift Out pulse may be applied.

2. Shift Out goes HIGH causing the next step.

3. Output Ready goes LOW.

4. The read pointer is incremented.

5. Output Ready goes HIGH indicating that new data (B) is now available at the FIFO outputs.

6. If the FIFO has only one word loaded (A DATA) then Output Ready stays LOW and the A DATA remains unchanged at the outputs.

7. Shift Out pulses applied when Output Ready is LOW will be ignored.

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SHIFT OUT

OUTPUT DATA

OUTPUT READY

A-DATA

B-DATA

(1)

C-DATA

(2)

NOTES:

1. This data is loaded consecutively A, B, C.

2. Data is shifted out when Shift Out makes a HIGH to LOW transition.

Figure 5. Output TIming

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SHIFT IN

INPUT DATA

INPUT READY

STABLE DATA

(1)

(3)

(4)

(5)

SHIFT OUT

(2)

NOTES:

1. FIFO is initially full.

2. Shift Out pulse is applied.

3. Shift In is held HIGH.

4. As soon as Input Ready becomes HIGH the Input Data is loaded into the FIFO.

Figure 4. Data is Shifted In Whenever Shift In and Input Ready are Both HIGH