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IDT72274L20TF Datasheet(PDF) 4 Page - Integrated Device Technology |
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IDT72274L20TF Datasheet(HTML) 4 Page - Integrated Device Technology |
4 / 31 page 4 IDT72264/72274 VARIABLE WIDTH SUPERSYNC FIFO ™ (8192 x 18 or 16384 x 9) and (16384 x 18 or 32768 x 9) COMMERCIAL TEMPERATURE RANGES Symbol Name I/O Description D0–D17 Data Inputs I Data inputs for a 18-bit bus. MRS Master Reset I MRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Master Reset, the FIFO is configured for either FWFT or IDT Standard Mode, one of two programmable flag default settings, and serial or parallel programming of the offset settings. PRS Partial Reset I PRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Partial Reset,the existing mode (IDT or FWFT), programming method (serial or parallel), and programmable flag settings are all retained. RT Retransmit I Allows data to be resent starting with the first location of FIFO memory. FWFT/SI First Word Fall I During Master Reset, selects First Word Fall Through or IDT Standard mode. Through/Serial In After Master Reset, this pin functions as a serial input for loading offset registers WCLK Write Clock I When enabled by WEN, the rising edge of WCLK writes data into the FIFO and offsets into the programmable registers. WEN Write Enable I WEN enables WCLK for writing data into the FIFO memory and offset registers. RCLK Read Clock I When enabled by REN, the rising edge of RCLK reads data from the FIFO memory and offsets from the programmable registers. REN Read Enable I REN enables RCLK for reading data from the FIFO memory and offset registers. OE Output Enable I OE controls the output impedance of Qn. SEN Serial Enable I SEN enables serial loading of programmable flag offsets. LD Load I During Master Reset, LD selects one of two partial flag default offsets (127 and 1023) and determines programming method, serial or parallel. After Master Reset, this pin enables writing to and reading from the offset registers. MAC Memory Array I MAC selects 8192 x 18 or 16384x 9 memory array organization for the IDT72264. Configuration It selects 16384 x 18 or 32678 x 9 memory array organization for the IDT72274. FS Frequency Select I FS selects selects WCLK or RCLK, whichever is running at a higher frequency, to synchronize the FIFO's internal state machine. FF/IR Full Flag/ O In the IDT Standard Mode, the FF function is selected. FF indicates whether or Input Ready not the FIFO memory is full. In the FWFT mode, the IR function is selected. IR indicates whether or not there is space available for writing to the FIFO memory. EF/OR Empty Flag/ O In the IDT Standard Mode, the EF function is selected. EF indicates whether or Output Ready not the FIFO memory is empty. In FWFT mode, the OR function is selected. OR indicates whether or not there is valid data available at the outputs. PAF Programmable O PAF goes HIGH if the number of free locations in the FIFO memory is more than Almost Full Flag offset m which is stored in the Full Offset register. PAFgoes LOW if the number of free locations in the FIFO memory is less than m. PAE Programmable O PAE goes LOW if the number of words in the FIFO memory is less than offset n Almost Empty which is stored in the Empty Offset register. PAE goes HIGH if the number of Flag words in the FIFO memory is greater than offset n. HF Half-full Flag O HF indicates whether the FIFO memory is more or less than half-full. Q0–Q17 Data Outputs O Data outputs for a 18-bit bus. VCC Power +5 volt power supply pins. GND Ground Ground pins. PIN DESCRIPTION |
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