CMOS CLOCKED FIFO WITH

BUS-MATCHING AND

BYTE SWAPPING 64 x 36

2002 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.

DSC-3145/1

IDT723613

MARCH 2002

IDT and the IDT logo are registered trademarks of Integrated Device Technology Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

1

©

FEATURES:

coincident (permits simultaneous reading and writing of data on

a single clock edge)

Port B

and 9 bits (byte)

sizes

120-pin thin quad flatpack (TQFP)

°°°°°C to +85°°°°°C) is available

DESCRIPTION:

The IDT723613 is a monolithic, high-speed, low-power, CMOS synchro-

nous (clocked) FIFO memory which supports clock frequencies up to 67 MHz

and has read-access times as fast as 10 ns. The 64 x 36 dual-port SRAM FIFO

buffers data from port A to port B. The FIFO has flags to indicate empty and full

conditions, and two programmable flags, Almost-Full (

AF)andAlmost-Empty

(

AE),toindicatewhenaselectednumberofwordsisstoredinmemory.FIFO

data on port B can be output in 36-bit, 18-bit, and 9-bit formats with a choice of

big- or Little-Endian configurations. Three modes of byte-order swapping are

possible with any bus-size selection. Communication between each port can

bypass the FIFO via two 36-bit mailbox registers. Each mailbox register has

a flag to signal when new mail has been stored. Parity is checked passively

FUNCTIONAL BLOCK DIAGRAM

Mail 2

Register

Mail 1

Register

64 x 36

Write

Pointer

Read

Pointer

Status Flag

Logic

CLKA

CSA

W/

RA

ENA

MBA

Port-A

Control

Logic

Device

Control

RST

PEFA

MBF2

Port-B

Control

Logic

MBF1

EF

AE

36

FF

AF

3145 drw01

Programmable

Flag Offset

Registers

Parity

Gen/Check

FIFO

ODD/

EVEN

PGA

Parity

Gen/Check

PGB

PEFB

36

RAM ARRAY

64 x 36

CLKB

CSB

W/

RB

ENB

BE

SIZ0

SIZ1

SW0

SW1

Port-B

Control

Logic