8

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT723613 CMOS CLOCKED FIFO WITH

BUS-MATCHING AND BYTE SWAPPING 64 x 36

AC ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF

SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE

Commercial

IDT723613L15

IDT723613L20

Symbol

Parameter

Min.

Max.

Min.

Max.

Unit

Clock Frequency, CLKA or CLKB

–

66.7

–

50

MHz

Clock Cycle Time, CLKA or CLKB

15

–

20

–

ns

Pulse Duration, CLKA and CLKB HIGH

6

–

8

–

ns

Pulse Duration, CLKA and CLKB LOW

6

–

8

–

ns

4–

5

–

ns

Setup Time,

CSA, W/RA, ENA, and MBA before CLKA

↑; CSB,W/RB, and ENB before

5

–

5

–

ns

CLKB

↑

Setup Time, SIZ0, SIZ1,and BE before CLKB

↑

4–

5

–

ns

Setup Time, SW0 and SW1 before CLKB

↑

5–

7

–

ns

Setup Time, ODD/

EVEN and PGB before CLKB

4–

5

–

ns

Setup Time,

RST LOW before CLKA

5–

6

–

ns

Setup Time, FS0 and FS1 before

RST HIGH

5

–

6

–

ns

1–

1

–

ns

Hold Time,

CSA W/RA, ENA and MBA after CLKA

↑; CSB, W/RB, and ENB after CLKB↑

1–

1

–

ns

Hold Time, SIZ0, SIZ1, and

BE after CLKB

↑

2–

2

–

ns

Hold Time, SW0 and SW1 after CLKB

↑

0–

0

–

ns

Hold Time, ODD/

EVEN and PGB after CLKB

0–

0

–

ns

Hold Time,

RST LOW after CLKA

5–

6

–

ns

Hold Time, FS0 and FS1 after

RST HIGH

4

–

4

–

ns

↑ and CLKB↑ for EF and FF

8–

8

–

ns

↑ and CLKB↑ for AE and AF

14

–

16

–

ns

NOTES:

1. Industrial temperature range product for 20ns speed grade is available as a standard device. All other speed grades are available by special order.

2. Only applies for a clock edge that does a FIFO read.

3. Requirement to count the clock edge as one of at least four needed to reset a FIFO.

4. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.