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IDT723613L30PQF Datasheet(PDF) 8 Page - Integrated Device Technology |
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IDT723613L30PQF Datasheet(HTML) 8 Page - Integrated Device Technology |
8 / 26 page 8 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDT723613 CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 AC ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE Commercial Com’l & Ind’l(1) IDT723613L15 IDT723613L20 Symbol Parameter Min. Max. Min. Max. Unit fS Clock Frequency, CLKA or CLKB – 66.7 – 50 MHz tCLK Clock Cycle Time, CLKA or CLKB 15 – 20 – ns tCLKH Pulse Duration, CLKA and CLKB HIGH 6 – 8 – ns tCLKL Pulse Duration, CLKA and CLKB LOW 6 – 8 – ns tDS Setup Time, A0-A35 before CLKA ↑ and B0-B35 before CLKB↑ 4– 5 – ns tENS Setup Time, CSA, W/RA, ENA, and MBA before CLKA ↑; CSB,W/RB, and ENB before 5 – 5 – ns CLKB ↑ tSZS Setup Time, SIZ0, SIZ1,and BE before CLKB ↑ 4– 5 – ns tSWS Setup Time, SW0 and SW1 before CLKB ↑ 5– 7 – ns tPGS Setup Time, ODD/ EVEN and PGB before CLKB ↑(2) 4– 5 – ns tRSTS Setup Time, RST LOW before CLKA ↑ or CLKB↑(3) 5– 6 – ns tFSS Setup Time, FS0 and FS1 before RST HIGH 5 – 6 – ns tDH Hold Time, A0-A35 after CLKA ↑ and B0-B35 after CLKB↑ 1– 1 – ns tENH Hold Time, CSA W/RA, ENA and MBA after CLKA ↑; CSB, W/RB, and ENB after CLKB↑ 1– 1 – ns tSZH Hold Time, SIZ0, SIZ1, and BE after CLKB ↑ 2– 2 – ns tSWH Hold Time, SW0 and SW1 after CLKB ↑ 0– 0 – ns tPGH Hold Time, ODD/ EVEN and PGB after CLKB ↑(2) 0– 0 – ns tRSTH Hold Time, RST LOW after CLKA ↑ or CLKB↑(3) 5– 6 – ns tFSH Hold Time, FS0 and FS1 after RST HIGH 4 – 4 – ns tSKEW1(4) Skew Time, between CLKA ↑ and CLKB↑ for EF and FF 8– 8 – ns tSKEW2(4) Skew Time, between CLKA ↑ and CLKB↑ for AE and AF 14 – 16 – ns NOTES: 1. Industrial temperature range product for 20ns speed grade is available as a standard device. All other speed grades are available by special order. 2. Only applies for a clock edge that does a FIFO read. 3. Requirement to count the clock edge as one of at least four needed to reset a FIFO. 4. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle. (Commercial: VCC = 5.0V ±10%, TA = 0 °C to +70°C; Industrial; VCC = 5.0V ± 10%,TA = 40°C to +85°C) |
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