IDT723612L30PQF datasheet(4/29 Pages) IDT

Part #	IDT723612L30PQF

Description	BiCMOS SyncBiFIFOO 64 x 36 x 2

Download	29 Pages

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Manufacturer	IDT [Integrated Device Technology]

Direct Link	http://www.idt.com

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COMMERCIAL TEMPERATURE RANGE

IDT723612 BiCMOS SyncBiFIFO

™

64 x 36 x 2

Symbol

Name

I/O

Description

A0-A35

Port-A Data

I/O

36-bit bidirectional data port for side A.

AEA

Almost-Empty Flag

O

Programmable almost-empty flag synchronized to CLKA. It is LOW when

(Port A)

the number of words in the FIFO2 is less than or equal to the value in the

offset register, X.

AEB

Port-B Almost-Empty

O

Programmable almost-full flag synchronized to CLKB. It is LOW when the

Flag

(PortB)

number of words in FIFO1 is less than or equal to the value in the

offset register, X.

AFA

Port-A Almost-Full

O

Programmable almost-full flag synchronized to CLKA. It is LOW when the

Flag

(Port A)

number of empty locations in FIFO1 is less than or equal to the value in the

offset register, X.

AFB

Port-B Almost-Empty

O

Programmable almost-full flag synchronized to CLKB. It is LOW when the

Flag

(Port B)

number of empty locations in FIFO2 is less than or equal to the value in the

offset register, X.

B0-B35

Port-B Data.

I/O

36-bit bidirectional data port for side B.

CLKA

Port-A Clock

I

CLKA is a continuous clock that synchronizes all data transfers through port-

A and can be aynchronous or coincident to CLKB.

EFA, FFA, AFA, and AEA

are synchronized to the LOW-to-HIGH transition of CLKA.

CLKB

Port-B Clock

I

CLKB is a continuous clock that synchronizes all data transfers through port-

B and can be asynchronous or coincident to CLKA.

EFB, FFB, AFB, and

AEB are synchronized to the LOW-to-HIGH transition of CLKB.

CSA

Port-A Chip Select

I

CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or

write data on port-A. The A0-A35 outputs are in the high-impedance state

when

CSA is HIGH.

CSB

Port-B Chip Select

I

B must be LOW to enable a LOW-to-HIGH transition of CLKB to read or

write data on port-B. The B0-B35 outputs are in the high-impedance state

when

CSB is HIGH.

EFA

Port-A Empty Flag

O

EFA is synchronized to the LOW-to-HIGH transition of CLKA. When EFA is

(Port A)

LOW, FIFO2 is empty, and reads from its memory are disabled. Data can

be read from FIFO2 to the output register when

EFA is HIGH. EFA is forced

LOW when the device is reset and is set HIGH by the second LOW-to-HIGH

transition of CLKA after data is loaded into empty FIFO2 memory.

EFB

Port-B Empty Flag

O

EFB is synchronized to the LOW-to-HIGH transition of CLKB. When EFB is

(Port B)

LOW, the FIFO1 is empty, and reads from its memory are disabled. Data

can be read from FIFO1 to the output register when

EFB is HIGH. EFB is

forced LOW when the device is reset and is set HIGH by the second LOW-

to-HIGH transition of CLKB after data is loaded into empty FIFO1 memory.

ENA

Port-A Enable

I

ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or

write data on port-A.

ENB

Port-B Enable

I

ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or

write data on port-B.

FFA

Port-A Full Flag

O

FFA is synchronized to the LOW-to-HIGH transition of CLKA. When FFA is

(Port A)

LOW, FIFO1 is full, and writes to its memory are disabled.

FFA is forced

LOW when the device is reset and is set HIGH by the second LOW-to-HIGH

transition of CLKA after reset.

FFB

Port-B Full Flag

O

FFB is synchronized to the LOW-to-HIGH transition of CLKB. When FFB is

(Port B)

LOW, FIFO2 is full, and writes to its memory are disabled.

FFB is forced

LOW when the device is reset and is set HIGH by the second LOW-to-HIGH

transition of CLKB after reset.

FS1, FS0 Flag-Offset Selects

I

The LOW-to-HIGH transition of

RST latches the values of FS0 and FS1,

which selects one of four preset values for the almost-full flag and almost-

empty flag.

MBA

Port-A Mailbox Select

I

A HIGH level on MBA chooses a mailbox register for a port-A read or write

operation. When the A0-A35 outputs are active, a HIGH level on MBA

selects data from the mail2 register for output, and a LOW level selects

FIFO2 output register data for output.

PIN DESCRIPTION

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