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IDT7025S15PFB Datasheet(PDF) 10 Page - Integrated Device Technology

Part # IDT7025S15PFB
Description  HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT7025S15PFB Datasheet(HTML) 10 Page - Integrated Device Technology

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6.16
10
IDT7025S/L
HIGH-SPEED 8K x 16 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/
W
W
W
W
W CONTROLLED TIMING(1,5,8)
TIMING WAVEFORM OF WRITE CYCLE NO. 2,
CE
CE
CE
CE
CE, UB
UB
UB
UB
UB, LB
LB
LB
LB
LB CONTROLLED TIMING(1,5)
2683 drw 10
tWC
tAS
tWR
tDW
tDH
ADDRESS
DATAIN
R/
W
tAW
tEW
UB or LB
(3)
(2)
(6)
CE or SEM
(9)
(9)
R/
W
tWC
tHZ
tAW
tWR
tAS
tWP
DATAOUT
(2)
tWZ
tDW
tDH
tOW
OE
ADDRESS
DATAIN
(6)
(4)
(4)
(7)
UB or LB
2683 drw 09
(9)
CE or SEM
(9)
(7)
(3)
NOTES:
1. R/
W or CE or UB & LB must be High during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a Low
UB or LB and a Low CE and a Low R/W for memory array writing cycle.
3. tWR is measured from the earlier of
CE or R/W (or SEM or R/W) going High to the end-of-write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the
CE or SEM Low transition occurs simultaneously with or after the R/W Low transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last,
CE, R/W, or byte control.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured +/- 500mV from steady state with Output
Test Load (Figure 2).
8. If
OE is Low during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data
to be placed on the bus for the required tDW. If
OE is High during an R/W controlled write cycle, this requirement does not apply and the write pulse can
be as short as the specified tWP.
9. To access RAM,
CE = VIL, UB or LB = VIL, and SEM = VIH. To access Semaphore, CE = VIH or UB & LB = VIL, and SEM = VIL. tEW must be met
for either condition.


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