IDT7024L15PFB datasheet(6/20 Pages) IDT

Part #	IDT7024L15PFB

Description	HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM

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Manufacturer	IDT [Integrated Device Technology]

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6.15

6

IDT7024S/L

HIGH-SPEED 4K x 16 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER THE

OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(1)(Cont.) (VCC = 5.0V

± 10%)

7024X35

7024X55

7024X70

Test

Mil. Only

Symbol

Parameter

Condition

Version

Typ.

(2)

Max.

Typ.

(2)

Max. Typ.

(2)

Max. Unit

ICC

Dynamic Operating

CE = VIL, Outputs Open

MIL.

S

150

300

150

300

140

300

mA

Current

SEM = VIH

L

150

250

150

250

140

250

(Both Ports Active)

f = fMAX

(3)

COM’L.

S

150

250

150

250

—

L

150

210

150

210

—

ISB1

Standby Current

CEL = CER = VIH

MIL.

S

13

80

13

80

10

80

mA

(Both Ports — TTL

SEMR = SEML = VIH

L

13

65

13

651065

Level Inputs)

f = fMAX

(3)

COM’L.

S

13

60

13

60

—

L13

50

13

50

—

ISB2

Standby Current

CE"A"=VIL and CE"B"=VIH(5)

MIL.

S

85

190

85

190

80

190

mA

(One Port — TTL

Active Port Outputs Open

L

85

160

85

160

80

160

Level Inputs)

f = fMAX

(3)

COM’L.

S

85

155

85

155

—

SEMR = SEML = VIH

L

85

130

85

130

—

ISB3

Full Standby Current

Both Ports

CEL and

MIL.

S

1.0

30

1.0

30

1.0

30

mA

(Both Ports — All

CER > VCC - 0.2V

L

0.2

10

0.2

10

0.2

10

CMOS Level Inputs)

VIN > VCC - 0.2V or

COM’L.

S

1.0

15

1.0

15

—

VIN < 0.2V, f = 0

(4)

L

0.2

5

0.2

5

—

SEMR = SEML > VCC - 0.2V

ISB4

Full Standby Current

CE"A" < 0.2 and

MIL.

S

80

175

80

175

75

175

mA

(One Port — All

CE"B" > VCC - 0.2V(5)

L

80

150

80

150

75

150

CMOS Level Inputs)

SEMR = SEML > VCC - 0.2V

VIN > VCC - 0.2V or

COM’L.

S

80

135

80

135

—

VIN < 0.2V,

L

80

110

80

110

—

Active Port Outputs Open,

f = fMAX

(3)

NOTES:

2740 tbl 10

1. "X" in part numbers indicates power rating (S or L).

2. VCC = 5V, TA = +25

°C, and are not production tested. ICCDC = 120mA (typ.)

3. At f = fMAX

, address and I/O'S are cycling at the maximum frequency read cycleof 1/tRC, and using “AC Test Conditions”of input levels of GND to 3V.

4. f = 0 means no address or control lines change.

5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES (L Version Only)

(VLC = 0.2V, VHC = VCC - 0.2V)(4)

Symbol

Parameter

Test Condition

Min.

Typ.

(1)

Max.

Unit

VDR

VCC for Data Retention

VCC = 2V

2.0

—

V

ICCDR

Data Retention Current

CE > VHC

MIL.

—

100

4000

µA

VIN > VHC or < VLC

COM’L.

—

100

1500

tCDR

(3)

Chip Deselect to Data Retention Time

SEM > VHC

0—

—

ns

tR

(3)

Operation Recovery Time

tRC

(2)

——

ns

NOTES:

2740 tbl 11

1. TA = +25

°C, VCC = 2V, and are by characterization but are not production tested.

2. tRC = Read Cycle Time

3. This parameter is guaranteed by device characterization but are not production tested.

4

. At Vcc < 2.0V, input leakages are not defined.

DATA RETENTION MODE

VCC

CE

2740 drw 05

4.5V

tCDR

tR

VIH

VDR

VIH

4.5V

VDR

2V

≥

DATA RETENTION WAVEFORM

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