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IDT7223611L30PQF Datasheet(PDF) 11 Page - Integrated Device Technology |
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IDT7223611L30PQF Datasheet(HTML) 11 Page - Integrated Device Technology |
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11 / 20 page  IDT723611 CMOS SyncFIFO ™ 64 x 36 COMMERCIAL TEMPERATURE RANGES 11 empty offset register (X). This register is loaded with one of four preset values during a device reset (see reset above). The almost-full flag is LOW when the FIFO contains (64-X) or more words in memory and is HIGH when the FIFO contains [64-(X+1)] or less words. Two LOW-to-HIGH transitions on the port-A clock (CLKA) are required after a FIFO read for the almost-full flag to reflect the new level of fill. Therefore, the almost-full flag of a FIFO containing [64-(X+1)] or less words remains LOW if two CLKA cycles have not elapsed since the read that reduced the number of words in memory to [64-(X+1)]. The almost-full flag is set HIGH by the second CLKA LOW-to-HIGH transition after the FIFO read that reduces the number of words in memory to [64-(X+1)]. A LOW-to-HIGH transition on CLKA begins the first synchronization cycle if it occurs at time tSKEW2 or greater after the read that reduces the number of words in memory to [64-(X+1)]. Otherwise, the subsequent CLKA cycle can be the first synchronization cycle (see figure 7). MAILBOX REGISTERS Two 36-bit bypass registers are on the IDT723611 to pass command and control information between port A and port B. The mailbox-select (MBA, MBB) inputs choose between a mail register and a FIFO for a port data transfer operation. A LOW-to-HIGH transition on CLKA writes A0-A35 data to the mail1 register when port-A write is selected by CSA, W/RA, and ENA with MBA HIGH. A LOW-to-HIGH transition on CLKB writes B0-B35 data to the mail2 register when port-B write is selected by CSB, W/RB, and ENB with MBB HIGH. Writing data to a mail register sets its corresponding flag ( MBF1 or MBF2) LOW. Attempted writes to a mail register are ignored while its mail flag is LOW. When the port-B data (B0-B35) outputs are active, the data on the bus comes from the FIFO output register when the port- B mailbox select (MBB) input is LOW and from the mail1 register when MBB is HIGH. Mail2 data is always present on the port-A data (A0-A35) outputs when they are active. The mail1 register flag ( MBF1) is set HIGH by a LOW-to-HIGH transition on CLKB when a port-B read is selected by CSB, W/ RB, and ENB with MBB HIGH. The mail2 register flag (MBF2) is set HIGH by a LOW-to-HIGH transition on CLKA when a port-A read is selected by CSA, W/RA, and ENA with MBA HIGH. The data in a mail register remains intact after it is read and changes only when new data is written to the register. PARITY CHECKING The port-A (A0-A35) inputs and port-B (B0-B35) inputs each have four parity trees to check the parity of incoming (or outgoing) data. A parity failure on one or more bytes of the input bus is reported by a LOW level on the port parity error flag ( PEFA, PEFB). Odd or even parity checking can be selected, and the parity error flags can be ignored if this feature is not desired. Parity status is checked on each input bus according to the level of the odd/even parity (ODD/ EVEN) select input. A parity error on one or more bytes of a port is reported by a LOW level on the corresponding port parity error flag ( PEFA, PEFB) output. Port-A bytes are arranged as A0-A8, A9-A17, A18- A26, and A27-A35, and port-B bytes are arranged as B0-B8, B9-B17, B18-B26, and B27-B35. When odd/even parity is selected, a port parity error flag ( PEFA, PEFB) is LOW if any byte on the port has an odd/even number of LOW levels applied to its bits. The four parity trees used to check the A0-A35 inputs are shared by the mail2 register when parity generation is se- lected for port-A reads (PGA=HIGH). When port-A read from the mail2 register with parity generation is selected with CSA LOW, ENA HIGH, W/ RA LOW, MBA HIGH, and PGA HIGH, the port-A parity error flag ( PEFA) is held HIGH regardless of the levels applied to the A0-A35 inputs. Likewise, the parity trees used to check the B0-B35 inputs are shared by the mail1 register when parity generation is selected for port-B reads (PGB=HIGH). When a port-B read from the mail1 register with parity generation is selected with CSB LOW, ENB HIGH, W/ RB LOW, MBB HIGH, and PGB HIGH, the port-B parity error flag ( PEFB) is held HIGH regardless of the levels applied to the B0-B35 inputs. PARITY GENERATION A HIGH level on the port-A parity generate select (PGA) or port-B generate select (PGB) enables the IDT723611 to generate parity bits for port reads from a FIFO or mailbox register. Port-A bytes are arranged as A0-A8, A9-A17, A18- A26, and A27-A35, with the most significant bit of each byte used as the parity bit. Port-B bytes are arranged as B0-B8, B9- B17, B18-B26, and B27-B35, with the most significant bit of each byte used as the parity bit. A write to a FIFO or mail register stores the levels applied to all thirty-six inputs regard- less of the state of the parity generate select (PGA, PGB) inputs. When data is read from a port with parity generation selected, the lower eight bits of each byte are used to generate a parity bit according to the level on the ODD/ EVEN select. The generated parity bits are substituted for the levels origi- nally written to the most significant bits of each byte as the word is read to the data outputs. Parity bits for FIFO data are generated after the data is read from SRAM and before the data is written to the output register. Therefore, the port-B parity generate select (PGB) and ODD/ EVEN have setup and hold time constraints to the port-B clock (CLKB) for a rising edge of CLKB used to read a new word to the FIFO output register. The circuit used to generate parity for the mail1 data is shared by the port-B bus (B0-B35) to check parity and the circuit used to generate parity for the mail2 data is shared by the port-A bus (A0-A35) to check parity. The shared parity trees of a port are used to generate parity bits for the data in a mail register when the port write/read select (W/ RA, W/RB) input is LOW, the port mail select (MBA, MBB) input is HIGH, chip select ( CSA, CSB) is LOW, enable (ENA, ENB) is HIGH, and the port parity generate select (PGA, PGB) is HIGH. Generating parity for mail register data does not change the contents of the register. |
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