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IDT71V321L25TF Datasheet(PDF) 9 Page - Integrated Device Technology |
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IDT71V321L25TF Datasheet(HTML) 9 Page - Integrated Device Technology |
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9 / 14 page  6.42 IDT71V321/71V421S/L High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges 9 AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(6) NOTES: 1. Port-to-port delay through RAM cells from the writing port to the reading port, refer to “Timing Waveform of Write with Port-to-Port Read and BUSY." 2. To ensure that the earlier of the two ports wins. 3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual). 4. To ensure that a write cycle is inhibited on port "B" during contention on port "A". 5. To ensure that a write cycle is completed on port "B" after contention on port "A". 6. 'X' in part numbers indicates power rating (S or L). 71V321X25 71V421X25 Com'l & Ind 71V321X35 71V421X35 Com'l Only 71V321X55 71V421X55 Com'l Only Symbol Parameter Min. Max. Min. Max. Min. Max. Unit BUSY Timing (For Master IDT71V321 Only) tBAA BUSY Access Time from Address ____ 20 ____ 20 ____ 30 ns tBDA BUSY Disable Time from Address ____ 20 ____ 20 ____ 30 ns tBAC BUSY Access Time from Chip Enable ____ 20 ____ 20 ____ 30 ns tBDC BUSY Disable Time from Chip Enable ____ 20 ____ 20 ____ 30 ns tWH Write Hold After BUSY(5) 12 ____ 15 ____ 20 ____ ns tWDD Write Pulse to Data Delay (1) ____ 50 ____ 60 ____ 80 ns tDDD Write Data Valid to Read Data Delay(1) ____ 35 ____ 45 ____ 65 ns tAPS Arbitration Priority Set-up Time(2) 5 ____ 5 ____ 5 ____ ns tBDD BUSY Disable to Valid Data (3) ____ 30 ____ 30 ____ 45 ns BUSY Timing (For Slave IDT71V421 Only) tWB BUSY Input to Write(4) 0 ____ 0 ____ 0 ____ ns tWH Write Hold After BUSY(5) 12 ____ 15 ____ 20 ____ ns tWDD Write Pulse to Data Delay(1) ____ 50 ____ 60 ____ 80 ns tDDD Write Data Valid to Read Data Delay(1) ____ 35 ____ 45 ____ 65 ns 3026 tbl 11 tWC tWP tDW tDH tBDD tDDD tBDA tWDD ADDR"B" DATAOUT"B" DATAIN"A" ADDR"A" MATCH VALID MATCH VALID R/W"A" BUSY"B" tAPS 3026 drw 10 (1) tBAA Timing Waveform of Write with Port-to-Port Read and BUSY(2,3,4) NOTES: 1. To ensure that the earlier of the two ports wins. tAPS is ignored for SLAVE (71V421). 2. CEL = CER = VIL 3. OE = VIL for the reading port. 4. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is opposite from port "A". |
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