4

IDT723611 CMOS SyncFIFO

™

64 x 36

COMMERCIAL TEMPERATURE RANGES

Symbol

Name

I/O

Description

A0-A35

Port-A Data

I/O 36-bit bidirectional data port for side A.

AE

Almost-Empty Flag

O

Programmable almost-empty flag synchronized to CLKB. It is LOW when

the number of words in the FIFO is less than or equal to the value in the offset

register, X.

AF

Almost-Full Flag.

O

Programmable almost-full flag synchronized to CLKA. It is LOW when the

number of empty locations in the FIFO is less than or equal to the value in the

offset register, X.

B0-B35

Port-B Data.

I/O 36-bit bidirectional data port for side B.

CLKA

Port-A Clock

I

CLKA is a continuous clock that synchronizes all data transfers through port-A

and can be aynchronous or coincident to CLKB.

FF and AF are synchronized

to the LOW-to-HIGH transition of CLKA.

CLKB

Port-B Clock

I

CLKB is a continuous clock that synchronizes all data transfers through port-B

and can be asynchronous or coincident to CLKA.

EF and AE are synchronized

to the LOW-to-HIGH transition of CLKB.

CSA

Port-A Chip Select

I

CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or

write data on port-A. The A0-A35 outputs are in the high-impedance state

when

CSA is HIGH.

CSB

Port-B Chip Select

I

CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or

write data on port-B. The B0-B35 outputs are in the high-impedance state

when

CSB is HIGH.

EF

Empty Flag

O

EF is synchronized to the LOW-to-HIGH transition of CLKB. When EF is LOW,

the FIFO is empty, and reads from its memory are disabled. Data can be read

from the FIFO to its output register when

EF is HIGH. EF is forced LOW when

the device is reset and is set HIGH by the second LOW-to-HIGH transition of

CLKB after data is loaded into empty FIFO memory.

ENA

Port-A Enable

I

ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or

write data on port-A.

ENB

Port-B Enable

I

ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or

write data on port-B.

FF

Full Flag

O

FF is synchronized to the LOW-to-HIGH transition of CLKA. When FF is LOW,

the FIFO is full, and writes to its memory are disabled.

FF is forced LOW when

the device is reset and is set HIGH by the second LOW-to-HIGH transition of

CLKA after reset.

FS1, FS0

Flag-Offset Selects

I

The LOW-to-HIGH transition of

RST latches the values of FS0 and FS1,

which loads one of four preset values into the almost-full and almost-empty

offset register (X).

MBA

Port-A Mailbox Select

I

A HIGH level on MBA chooses a mailbox register for a port-A read or write

operation.

MBB

Port-B Mailbox Select

I

A HIGH level on MBB chooses a mailbox register for a port-B read or write

operation. When the B0-B35 outputs are active, a HIGH level on MBB selects

data from the mail1 register for output, and a LOW level selects the FIFO

output register data for output.

MBF1

Mail1 Register Flag

O

MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to

the mail1 register. Writes to the mail1 register are inhibited while

MBF1 is set

LOW.

MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB when a port-B

read is selected and MBB is HIGH.

MBF1 is set HIGH when the device is

reset.

PIN DESCRIPTION