IDT7217L datasheet(8/13 Pages) IDT

Part #	IDT7217L

Description	16 x 16 PARALLEL CMOS MULTIPLIERS

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Manufacturer	IDT [Integrated Device Technology]

Direct Link	http://www.idt.com

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11.3

8

IDT7216L, IDT7217L

16 x 16 PARALLEL CMOS MULTIPLIERS

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS MILITARY (VCC = 5V

± 10%, TA = –55° to +125°C)

NOTES:

2580 tbl 07

1. To ensure that the correct product is entered in the output registers, new data may not be entered into the registers before the output registers have been

clocked.

2. Transition is measured

±500mV from steady state voltage.

3. Guaranteed by design, not production tested.

4. Minimum propagation delay times are guaranteed, not production tested.

5. This speed is available in PGA and Flatpack packages only.

7216L20(5)

7217L20

7216L25

7217L25

7216L30

7217L30

7216L40

7217L40

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

tMUC

Unclocked Multiply Time(4)

2

30

2

38

2

43

2

60

ns

tMC

Clocked Multiply Time(4)

2

30

2

25

2

30

2

40

ns

tS

X, Y, RND Set-up Time

11

—

12

—

12

—

15

—

ns

tH

X, Y, RND Hold Time

1

—

2

—

2

—

3

—

ns

tPWH

Clock Pulse Width High

9

—

10

—

10

—

15

—

ns

tPWL

Clock Pulse Width Low

9

—

10

—

10

—

15

—

ns

tPDSEL

MSPSEL to Product Out(4)

2

18

2

20

2

20

2

25

ns

tPDP

Output Clock to P(4)

2

18

2

20

2

20

2

25

ns

tPDY

Output Clock to Y(4)

2

18

2

20

2

20

2

25

ns

tENA

3-State Enable Time

—

18

—

20

—

20

—

25

ns

tDIS

3-State Disable Time(2)

—

20

—

22

—

22

—

25

ns

tS

Clock Enable Set-up Time (IDT7217 only)

10

—

10

—

10

—

12

—

ns

tH

Clock Enable Hold Time (IDT7217 only)

0

—

2

—

2

—

3

—

ns

tHCL

Clock Low Hold Time CLKXY Relative to

CLKML (IDT7216 only)(1,3)

0—

0

—

0—

0

—

ns

7216L55

7217L55

7216L65

7217L65

7216L75

7217L75

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

tMUC

Unclocked Multiply Time(4)

275

2

85

295

ns

tMC

Clocked Multiply Time(4)

255

2

65

275

ns

tS

X, Y, RND Set-up Time

20

—

25

—

25

—

ns

tH

X, Y, RND Hold Time

3

—

3

—

3

—

ns

tPWH

Clock Pulse Width High

15

—

15

—

15

—

ns

tPWL

Clock Pulse Width Low

15

—

15

—

15

—

ns

tPDSEL

MSPSEL to Product Out(4)

230

2

35

235

ns

tPDP

Output Clock to P(4)

230

2

30

235

ns

tPDY

Output Clock to Y(4)

230

2

30

235

ns

tENA

3-State Enable Time

—

25

—

35

—

40

ns

tDIS

3-State Disable Time(2)

—25

—

25

—25

ns

tS

Clock Enable Set-up Time (IDT7217 only)

15

—

15

—

15

—

ns

tH

Clock Enable Hold Time (IDT7217 only)

3

—

3

—

3

—

ns

tHCL

Clock Low Hold Time CLKXY Relative to CLKML

(IDT7216 only)(1,3)

0—

ns

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