5.35

10

COMMERCIAL TEMPERATURE RANGES

IDT72105, IDT72115, IDT72125,

256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO

Figure 12. A 3K x 16 Parallel-to-Serial FIFO using the IDT72125

2665 drw 15

EF

RSIX

RSOX

HF

FF

SOCP

FIFO #3

SO

W

FL/DIR

ADDRESS

DECODER

74FCT138

00

01

10

FULL

FLAG

HALF-FULL

FLAG

EMPTY

FLAG

HIGH AT RESET

EF

RSIX

RSOX

HF

FF

SOCP

FIFO #2

SO

W

FL/DIR

HIGH AT RESET

EF

RSIX

RSOX

HF

FF

SOCP

FIFO #1

SO

W

FL/DIR

LOW AT RESET

SERIAL OUTPUT CLOCK

SERIAL DATA

OUT

NOTE:

2665 tbl 10

1.

RS = Reset Input, FL/FIR = First Load/Direction, EF = Empty Flag Output, HF = Half- Full Flag Output, FF = Full Flag Output.

Table 2. Reset and First Load Truth Table–Width/Depth Compound Expansion Mode

Inputs

Internal Status

Outputs

Mode

RS

RS

FL

FL

DIR

Read Pointer

Write Pointer

EF

EF

HF

HF, FF

FF

Reset-First Device

0

0

X

Location Zero

Location Zero

0

1

Reset All Other Devices

0

1

X

Location Zero

Location Zero

0

1

Read/Write

1

X

0,1

X

X

X

X