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IDT7140SA35C Datasheet(PDF) 10 Page - Integrated Device Technology |
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IDT7140SA35C Datasheet(HTML) 10 Page - Integrated Device Technology |
10 / 14 page IDT7130SA/LA AND IDT7140SA/LA HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS MILITARY AND COMMERCIAL TEMPERATURE RANGES 6.01 10 TIMING WAVEFORM OF WRITE WITH BUSY BUSY BUSY BUSY BUSY(3) BUSY'B' 2689 drw 13 R/ W'A' tWP tWH tWB R/ W'B' (2) (1) NOTES: 1. tWH must be met for both BUSY Input (IDT7140, slave) or Output (IDT7130 master). 2. BUSY is asserted on port 'B' blocking R/W'B', until BUSY'B' goes High. 3. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is opposite from port "A". TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY CE CE CE CE CE TIMING (1) TIMING WAVEFORM OF BUSY ARBITRATION CONTROLLED BY ADDRESS MATCH TIMING (1) NOTES: 1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”. 2. If tAPS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (7130 only). tAPS ADDR 'A' AND 'B' ADDRESSES MATCH tBAC tBDC CE'B' CE'A' BUSY'A' 2689 drw 14 (2) BUSY'B' ADDRESSES DO NOT MATCH ADDRESSES MATCH tAPS ADDR'A' ADDR'B' 2689 drw 15 (2) tBAA tBDA tRC OR tWC |
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