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IDT71B74S15Y Datasheet(PDF) 6 Page - Integrated Device Technology |
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IDT71B74S15Y Datasheet(HTML) 6 Page - Integrated Device Technology |
6 / 9 page IDT71B74 BiCMOS STATIC RAM 64K (8K x 8-BIT) CACHE-TAG RAM COMMERCIAL TEMPERATURE RANGE 14.1 6 AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%) 71B74S8 71B74S10 71B74S12 71B74S15 71B74S20 Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit Write Cycle tWC Write Cycle Time 8 — 10 — 12 — 15 — 20 — ns tCW Chip Select to End of Write 7 — 8 — 9 — 10 — 15 — ns tAW Address Valid to End of Write 7 — 8 — 9 — 10 — 15 — ns tAS Address Set-up Time 0 — 0 — 0 — 0 — 0 — ns tWP Write Pulse Width 7 — 8 — 9 — 10 — 15 — ns tWR Write Recovery Time ( CS, WE) 0 — 0 —0 —0 —0 — ns tWHZ (1) Write Enable to Output in High-Z — 5 — 5 — 5 — 5 — 5 ns tDW Data Valid to End of Write 5 — 5 — 6 — 8 — 10 — ns tDH Data Hold from Write Time 0 — 0 — 0 — 0 — 0 — ns tOW (1) Output Active from End of Write 2 — 2 — 2 — 2 — 2 — ns NOTE: 3013 tbl 11 1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested. TIMING WAVEFORM OF WRITE CYCLE NO. 1 ( WE WE Controlled Timing, OE OE HIGH During Write) ( 1, 6) 3013 drw 11 CS OE tWC DATAOUT t AW t WR (3) ADDRESS WE t WP (2) DATAIN t DH t DW DATA VALID t OHZ (4,9) t WHZ (8,9) t AS t OW (9) NOTES: 1. WE, CS must be inactive during all address transitions. 2. A write occurs during the overlap of a LOW WE and a LOW CS. 3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle. 4. During this period, I/O pins are in the output state and input signals must not be applied. 5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 6. OE is continuously HIGH, OE ≥ VIH. If during the WE controlled write cycle the OE is LOW, tWP must be greater or equal to tWHZ + tDW to allow the I/O drivers to turn off and the data to be placed on the bus for the required tDW. If OE is HIGH during the WE controlled write cycle, this requirement does not apply and the minimum write pulse is the specified tWP. For a CS controlled write cycle, OE may be LOW with no degradation to tCW timing. 7. DATAOUT is never enabled, therefore the output is in High-Z state during the entire write cycle. 8. tWHZ is not included if OE remains HIGH during the write cycle. If OE is LOW during the Write Enabled write cycle then tWHZ must be added to tWP and tCW. 9. Transition is measured ±200mV from steady state. |
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