7

IDT71T024

LOW POWER 2V CMOS STATIC RAM 1 MEG (128K x 8-BIT)

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE CYCLE NO. 1 (

WE

WE CONTROLLED TIMING)

(1, 2, 5)

ADDRESS

CS1

WE

CS2

3779 drw 09

(6)

(7)

(6)

(6)

HIGH IMPEDANCE

(3)

(4)

(4)

CS1

ADDRESS

WE

CS2

3779 drw 10

(3)

TIMING WAVEFORM OF WRITE CYCLE NO. 2 (

CS1

CS1 AND CS2 CONTROLLED TIMING)

(1,2,5)

NOTES:

1.

WE or CS1 must be HIGH, or CS2 must be LOW during all address transitions.

2. A write occurs during the overlap of a LOW

CS1, HIGH CS2, and a LOW WE.

CS1 or WE going HIGH or CS2 going LOW to the end of the write cycle.

4. During this period, I/O pins are in the output state, and input signals must not be applied.

5. If the

CS1 LOW transition or CS2 HIGH transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.

6. Transition is measured

±200mV from steady state.

7.

OE is HIGH during a WE controlled write cycle, this requirement does not apply and the