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IDT7188L Datasheet(PDF) 7 Page - Integrated Device Technology |
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IDT7188L Datasheet(HTML) 7 Page - Integrated Device Technology |
7 / 8 page 6.42 IDT7188S/L CMOS Static RAM 64K (16K x 4-Bit) Military Temperature Range 7 Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,2,3,5) Ordering Information NOTES: 1. WE or CS must be HIGH during all address transitions. 2. A write occurs during the overlap (tWP) of a LOW CS and a LOW WE. 3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle. 4. During this period, I/O pins are in the output state so that the input signals should not be applied. 5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in the high-impedance state. 6. Transition is measured ±200mV from steady state. CS DATAIN ADDRESS WE ttWR 2989 drw 09 tAW tDW tWC tCW tDH tAS DATA VALID , X Power XX Speed X Package X Process/ Temperature Range B Military (-55°C to +125°C) Compliant to MIL-STD-883, Class B D 300 mil Ceramic DIP (D22-1) 25 35 45 55 70 85 S L Standard Power Low Power 7188 Speed in nanoseconds 2989 drw 10 Device Type , IDT |
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