6.17

10

IDT7026S/L

HIGH-SPEED 16K x 16 DUAL-PORT STATIC RAM

MILITARY AND COMMERCIAL TEMPERATURE RANGES

TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/

W

W

W

W

NOTES:

1. R/

W or CE or UB and LB must be HIGH during all address transitions.

CE and a LOW R/W for memory array writing cycle.

CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.

4. During this period, the I/O pins are in the output state and input signals must not be applied.

5. If the

CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal is asserted last,

CE or R/W.

7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured + 200mV from steady state with the Output

Test Load (Figure 2).

8. If

OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can

9. To access RAM,

TIMING WAVEFORM OF WRITE CYCLE NO. 2,

CE

CE

CE

CE

CE, UB

UB

UB

UB

UB, LB

LB

LB

LB

R/

W

(2)

OE

ADDRESS

(6)

(4)

(4)

(7)

UB or LB

2939 drw 08

(9)

CE or SEM

(9)

(7)

(3)

2939 drw 09

ADDRESS

R/

W

UB or LB

(3)

(2)

(6)

CE or SEM

(9)

(9)