6

IDT71256SA

CMOS Static RAM 256K (32K x 8-Bit)

Commercial and Industrial Temperature Ranges

NOTES:

1. A write occurs during the overlap of a LOW

CS and a LOW WE.

2.

OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as

3. During this period, I/O pins are in the output state, and input signals must not be applied.

4. If the

CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.

5. Transition is measured ±200mV from steady state.

ADDRESS

CS

WE

2948 drw 07

(5)

(3)

(3)

(2)

(5)

(5)

HIGH IMPEDANCE

,

CS

ADDRESS

WE

2948 drw 08

,