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IDT71256SA70 Datasheet(PDF) 5 Page - Integrated Device Technology

Part No. IDT71256SA70
Description  CMOS STATIC RAM 256K (32K x 8-BIT)
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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IDT71256SA70
CMOS STATIC RAM 256K (32K x 8-BIT)
COMMERCIAL TEMPERATURE RANGES
5
TIMING WAVEFORM OF READ CYCLE NO. 2
(1,2,4)
TIMING WAVEFORM OF WRITE CYCLE NO.1 (
WE
WE CONTROLLED TIMING)
(1,2,3,5)
NOTES:
1.
WE or CS must be HIGH during all address transitions.
2. A write occurs during the overlap of a LOW
CS and a LOW WE.
3.
OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn
off and data to be placed on the bus for the required tDW. If
OE is HIGH during a WE controlled write cycle, this requirement does not apply and the
minimum write pulse is as short as the specified tWP.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the
CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
6. Transition is measured
±200mV from steady state.
TIMING WAVEFORM OF WRITE CYCLE NO.2 (
CS
CS CONTROLLED TIMING)
(1,2,5)
NOTES:
1.
WE is HIGH for Read Cycle.
2. Device is continuously selected,
CS is LOW.
3. Address must be valid prior to or coincident with the later of
CS transition LOW; otherwise tAA is the limiting parameter.
4.
OE is LOW.
5. Transition is measured
±200mV from steady state.
DATAOUT
ADDRESS
3567 drw 07
tRC
tAA
tOH
tOH
DATAOUT VALID
PREVIOUS DATAOUT VALID
ADDRESS
CS
WE
DATAOUT
DATAIN
3567 drw 08
(6)
(4)
(4)
(3)
(6)
(6)
DATAIN VALID
HIGH IMPEDANCE
tWC
tAS
tWHZ
tWP
tCHZ
tOW
tDW
tWR
tAW
tDH
CS
ADDRESS
WE
3567 drw 09
DATAIN VALID
tAW
tWC
tCW
tAS
tWR
tDW
tDH
DATAIN




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