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IDT71256SA Datasheet(PDF) 5 Page - Integrated Device Technology

Part No. IDT71256SA
Description  CMOS STATIC RAM 256K (32K x 8-BIT)
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Maker  IDT [Integrated Device Technology]
Homepage  http://www.idt.com
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 5 page
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6.42
IDT71256SA
CMOS Static RAM 256K (32K x 8-Bit)
Commercial and Industrial Temperature Ranges
5
Timing Waveform of Read Cycle No. 1(1)
ADDRESS
OE
CS
DATAOUT
VCC SUPPLY
CURRENT
2948 drw 05
(5)
(5)
(5)
(5)
DATA
VALID
HIGH IMPEDANCE
tAA
tRC
tOE
tACS
tOLZ
tCHZ
tCLZ
(3)
tOHZ
OUT
tPU
tPD
ICC
ISB
,
Timing Waveform of Read Cycle No. 2(1,2,4)
NOTES:
1.
WE is HIGH for Read Cycle.
2. Device is continuously selected,
CS is LOW.
3. Address must be valid prior to or coincident with the later of
CS transition LOW; otherwise tAA is the limiting parameter.
4.
OE is LOW.
5. Transition is measured ±200mV from steady state.
DATAOUT
ADDRESS
2948 drw 06
tRC
tAA
tOH
tOH
DATAOUT VALID
PREVIOUS DATAOUT VALID
,




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