6.38

10

IDT70V24S/L

HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM

COMMERCIAL TEMPERATURE RANGE

BUSY TIMING (M/

0—

0—

0—

ns

Write Hold After

20

—

25

—

25

—

ns

PORT-TO-PORT DELAY TIMING

Write Pulse to Data Delay

(1)

—55

—

60

—80

ns

Write Data Valid to Read Data Delay

(1)

—50

—

55

—75

ns

AC ELECTRICAL CHARACTERISTICS OVER THE

IDT70V24X25

IDT70V24X35

IDT70V24X55

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

BUSY TIMING (M/

BUSY Access Time from Address Match

—

25

—

35

—

45

ns

BUSY Disable Time from Address Not Matched

—

25

—

35

—

45

ns

BUSY Access Time from Chip Low

—

25

—

35

—

45

ns

BUSY Disable Time from Chip High

—

25

—

35

—

45

ns

Arbitration Priority Set-up Time

(2)

5—

5—

5—

ns

—35

—

35

—40

ns

Write Hold After

20

—

25

—

25

—

ns

2911 drw 12

MATCH

R/

VALID

(1)

MATCH

VALID

TIMING WAVEFORM OF READ WITH

BUSY

BUSY

BUSY

BUSY

NOTES:

2740 tbl 13

1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Read With

BUSY (M / S = H)" or "Timing Waveform

of Write With Port-To-Port Delay (M /

S = L)".

2. To ensure that the earlier of the two ports wins.

4. To ensure that the write cycle is inhibited on port "B" during contention with port "A".

5. To ensure that a write cycle is completed on port "B" after contention with port "A".

6. "X" in part numbers indicates power rating (S or L).

NOTES:

2.

3.

4. If M/

5. All timing is the same for both left and right ports. Port "A" may be either the left or right Port. Port "B" is the port opposite from port "A".