Electronic Components Datasheet Search |
|
IDT70824L20G Datasheet(PDF) 3 Page - Integrated Device Technology |
|
IDT70824L20G Datasheet(HTML) 3 Page - Integrated Device Technology |
3 / 21 page 6.42 IDT70824S/L High-Speed 4K x 16 Sequential Access Random Access Memory Military and Commercial Temperature Ranges 3 Pin Descriptions: Random Access Port(1) Pin Descriptions: Sequential Access Port(1) NOTE: 1. "I/O" is bidirectional Input and Output. "I" is Input and "O" is Output. SYMBOL NAME I/O DESCRIPTION A0-A11 Address Lines I Address inputs to access the 4096-word (16-Bit) memory array. I/O0-I/O15 Inputs/Outputs I Random access data inputs/outputs for 16-Bit wide data. CE Chip Enable I When CE is LOW, the random access port is enabled. When CE is HIGH, the random access port is disabled into power-down mode and the I/O outputs are in the High-impedance state. All data is retained during CE = VIH, unless it is altered by the sequential port CE and CMD may not be LOW at the same time. CMD Control Register Enable I When CMD is LOW, address lines A0-A2, R/W, and inputs and outputs I/O0-I/O12, are used to access the control register, the flag register and the start and end of buffer registers. CMD and CE may not be LOW at the same time. R/ W Read/Write Enable I If CE is LOW and CMD is HIGH, data is written into the array when R/W is LOW and read out of the array when R/W is HIGH. If CE is HIGH and CMD is LOW, R/W is used to access the buffer command registers. CE and CMD may not be LOW at the same time. OE Output Enable I When OE is LOW and R/W is HIGH, I/O0-I/O15 outputs are enabled. When OE is HIGH, the I/O outputs are in the High-impedance state. LB, UB Lower Byte, Upper Byte Enables I When LB is LOW, I/O0-I/O7 are accessible for read and write operations. When LB is HIGH, I/O0-I/O7 are tri- stated and blocked during read and write operations. UB controls access for I/O8-I/O15 in the same manner and is asynchronous from LB. VCC Power Supply I Seven +5 power supply pins. All VCC pins must be connected to the same +5V VCC supply. GND Ground I Ten ground pins. All ground pins must be connected to the same ground supply. 3099 tbl 01 SYMBOL NAME I/O DESCRIPTION SI/O0-15 Inputs/Outputs I/O Sequential data inputs/outputs for 16-bit wide data. SCLK Clock I SI/O0-SI/O15, SCE, SR/W, and SLD are registered on the LOW-to-HIGH transition of SCLK. Also, the sequential access port address pointer increments by 1 on each LOW-TO-HIGH transition of SCLK when CNTEN is LOW. SCE Chip Enable I When SCE is LOW, the sequential access port is enabled on the LOW-to-HIGH transition of SCLK. When SCE is HIGH, the sequential access port is disabled into powered-down mode on the LOW-to-HIGH transition of SCLK, and the SI/O outputs are in the High-impedance state. All data is retained , unless altered by the random access port. CNTEN Counter Enable I When CNTEN is LOW, the address pointer increments on the LOW-to-HIGH transition of SCLK. This function is independent of CE. SR/ W Read/Write Enable I When SR/ W and SCE are LOW, a write cycle is initiated on the LOW-to-HIGH transition of SCLK. When SR/W is HIGH, and SCE and SOE are LOW, a read cycle is initiated on the LOW-to-HIGH transition of SCLK. Termination o f a write cycle is done on the LOW-to -HIGH transition of SCLK if SR/W or SCE is HIGH. SLD Address Pointer Load Control I When SLD is sampled LOW, there is an internal delay of one cycle before the address pointer changes. When SLD is LOW, data on the inputs SI/O0-SI/O11 is loaded into a data-in register on the LOW-to-HIGH transition of SCLK. On the Cycle following SLD, the address pointer charges to the address location contained in the data- in register. SSTRT1 and SSTRT2 may not be LOW while SLD is LOW or during the cycle following SLD. SSTRT1, SSTRT2 Load Start of Address Register I When SSTRT1 or SSTRT2 is LOW, the start of address register #1 or #2 is loaded into the address pointer on the LOW-to-HIGH transition of SCLK. The start addresses are stored in internal registers. SSTRT1 and SSTRT2 may not be LOW while SLD is LOW or during the cycle following SLD. EOB1, EOB2 End of Buffer Flag O EOB1 or EOB2 is output low when the address pointer is incremented to match the address stored in the end of buffer registers. The flags can be cleared by either asserting RST LOW or by writing zero into Bit 0 and/or Bit 1 of the control registe r at address 101. EOB1 and EOB2 are dependent on separate internal registers, and therefore separate match addresses. SOE Output Enable I SOE controls the data outputs and is independent of SCLK. When SOE is LOW, output buffers and the se quentially ad dressed data is output. When SOE is HIGH, the SI/O output bus is in the High-impedance state. SOE is asynchronous to SCLK. RST Reset I When RST is LOW, all internal registers are set to their default state, the address pointer is set to zero and the EOB1 and EOB2 flags are set HIGH. RST is asynchronous to SCLK. 3099 tbl 02 |
Similar Part No. - IDT70824L20G |
|
Similar Description - IDT70824L20G |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |